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1.发明公开SELECTIVE ERROR CORRECTING CODE AND MEMORY ACCESS GRANULARITY SWITCHING 有权选择性错误纠正代码和SPEICHERZUGANGSGRANULARITÄTSWECHSEL
公开(公告)号：EP2915045A1
公开(公告)日：2015-09-09
申请号：EP12887804.8
申请日：2012-11-02
发明人： LI, Sheng , JOUPPI, Norman Paul , YOON, Doe Hyun
CPC分类号： G06F11/0787 , G06F11/073 , G06F11/1048 , G06F12/0875 , G06F2212/45 , G11C7/20 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2029/0411
摘要： Example methods, systems, and apparatus to provide selective memory error protection and memory access granularity are disclosed herein. An example system includes a memory controller to determine a selected memory mode based on a request. The memory mode indicates that a memory page is to store a corresponding type of error protection information and is to store data for retrieval using a corresponding access granularity. The memory controller is to store the data and the error protection information in the memory page for retrieval using the error protection information and the access granularity.
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公开(公告)号：EP2891069A1
公开(公告)日：2015-07-08
申请号：EP12883648.3
申请日：2012-08-28
发明人： LI, Sheng , YOON, Doe Hyun , JOUPPI, Norman Paul
CPC分类号： G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F11/1471 , G06F12/0891 , G06F2003/0691 , G06F2212/1032 , G06F2212/202 , G06F2212/222 , G06F2212/251 , G06F2212/304 , G11C16/06
摘要： A method of performing data transactions in a high performance persistent memory comprising, with a processor, updating data by writing new data to non-volatile memory (NVM) and receiving a done signal from a transaction accelerator communicatively coupled to the NVM. An apparatus for high performance persistent memory, comprising a processor, a memory controller communicatively coupled to the processor, and non-volatile memory communicatively coupled to the memory controller and processor, the non-volatile memory comprising an ACID transaction accelerator, in which the processor updates data on the non-volatile memory (NVM) by writing new data to the NVM, and receives a done signal from the an ACID transaction accelerator when the data has been updated.
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公开(公告)号：EP2856471A1
公开(公告)日：2015-04-08
申请号：EP12877868.5
申请日：2012-05-31
发明人： UDIPI, Aniruddha Nagendran , MURALIMANOHAR, Naveen , JOUPPI, Norman Paul , DAVIS, Alan Lynn , BALASUBRAMONIAN, Rajeev
IPC分类号： G11C29/42
CPC分类号： G06F11/1064 , G06F11/1012 , G06F11/1044 , G06F11/108 , G11C2029/0411
摘要： A system may use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED may be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC, in response to identifying the error.
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公开(公告)号：EP2529374A2
公开(公告)日：2012-12-05
申请号：EP11737663.2
申请日：2011-01-27
发明人： MURALIMANOHAR, Naveen , UDIPI, Aniruddha Nagendran , CHATTERJEE, Niladrish , BALASUBRAMONIAN, Rajeev , DAVIS, Alan Lynn , JOUPPI, Norman Paul
IPC分类号： G11C11/4063 , G11C7/10 , G06F12/00
CPC分类号： G06F3/0625 , G06F3/0634 , G06F3/0658 , G06F3/0673 , G06F11/1088 , G06F12/0802 , G06F12/0893 , G06F2212/1028 , G06F2212/3042 , G06F2212/305 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/4082 , Y02D10/13
摘要： An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.
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公开(公告)号：EP2517058A1
公开(公告)日：2012-10-31
申请号：EP09852671.8
申请日：2009-12-21
发明人： TAN, Michael Renne Ty , BINKERT, Nathan Lorenzo , JOUPPI, Norman Paul , MCLAREN, Moray , AHN, Jung Ho
CPC分类号： G02B6/43 , G02B6/351 , G02B6/352 , G02B6/3528 , G02B6/3556 , G02B6/3596 , G02B6/3598
摘要： A circuit switched optical interconnection fabric includes a first hollow metal waveguide and a second hollow metal waveguide which intersects the first hollow metal waveguide to form an intersection. An optical element within the intersection is configured to selectively direct an optical signal between the first hollow metal waveguide and a second hollow metal waveguide.
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公开(公告)号：EP2992435A1
公开(公告)日：2016-03-09
申请号：EP13883432.0
申请日：2013-04-30
CPC分类号： G06F11/2094 , G06F11/08 , G06F11/10 , G06F11/1048 , G06F11/1076 , G06F2201/805 , G06F2201/85 , G06F2211/1059
摘要： According to an example, a resiliency group for a memory node in a memory network can provide error correction for a memory access in the memory node. The memory access may be received from a main memory controller of a processor connected to the memory network. The memory access may be executed by a memory controller of the memory node.
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公开(公告)号：EP2867897A1
公开(公告)日：2015-05-06
申请号：EP12880177.6
申请日：2012-06-28
CPC分类号： G11C11/5678 , G11C7/1057 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/06 , G11C16/26 , G11C2211/5642
摘要： A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from and write to the memory device, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.
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公开(公告)号：EP3005117A1
公开(公告)日：2016-04-13
申请号：EP13885657.0
申请日：2013-05-29
发明人： YOON, Doe Hyun , CHANG, Jichuan , MURALIMANOHAR, Naveen , RANGANATHAN, Parthasarathy , SCHREIBER, Robert , JOUPPI, Norman Paul
IPC分类号： G06F11/08
CPC分类号： G06F11/085 , G06F11/1048 , G06F11/1469 , G06F11/1471 , G06F17/30424
摘要： A detector detects, using an error code, an error in data stored in a memory. The detector determines whether the error is uncorrectable using the error code. In response to determining that the error is uncorrectable, an error handler associated with an application is invoked to handle the error in the data by recovering the data to an application-wide consistent state.
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公开(公告)号：EP2992438A1
公开(公告)日：2016-03-09
申请号：EP13883839.6
申请日：2013-04-30
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0611 , G06F3/0635 , G06F3/0659 , G06F3/0683 , G06F11/2064 , G06F11/2066 , G06F11/2069 , G06F11/2074 , G06F11/2082 , G06F11/3419 , G06F11/3457 , G06F11/3485 , G06F12/08 , G06F12/0811 , G06F13/382 , G06F2212/1016 , G06F2212/254
摘要： According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.
摘要翻译： 根据示例，存储器网络包括存储器节点。 存储器节点可以各自包括存储器和控制逻辑。 控制逻辑可以将存储器节点操作为由连接到存储器网络的处理器调用的存储器访问的目的地，并且可以将存储器节点作为路由器操作以将数据或存储器访问命令路由到存储器网络中的目的地。
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公开(公告)号：EP2992436A1
公开(公告)日：2016-03-09
申请号：EP13883783.6
申请日：2013-04-30
CPC分类号： G06F12/0835 , G06F12/0813 , G06F12/0815 , G06F12/0824 , G06F13/28 , G06F13/4022 , G06F13/4234 , G06F15/167 , G06F2212/1016 , G06F2212/1048 , G06F2212/621
摘要： According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.
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