-
-
公开(公告)号：EP4439562A1
公开(公告)日：2024-10-02
申请号：EP24164846.8
申请日：2024-03-12
发明人： YANG, Kiyeon , GU, Dongggeon , KOO, Bonwon , PARK, Jeonghee , SUNG, Hajun , AHN, Dongho , WUN, Zhe , LEE, Changseung , CHOI, Minwoo
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C2213/7320130101 , G11C13/003 , G11C2213/7120130101
摘要： Provided are a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or a memory apparatus including the self-selecting memory device. The memory device includes a first electrode, a second electrode apart from and facing the first electrode, and a memory layer between the first electrode and the second electrode. The memory layer has Ovonic threshold switching characteristics and is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed, the threshold voltage changing according to the polarity and the intensity of a bias voltage applied to the memory layer. Furthermore, an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer changing.
-
公开(公告)号：EP3607551B1
公开(公告)日：2024-09-18
申请号：EP18717670.6
申请日：2018-04-04
IPC分类号： G11C13/00
CPC分类号： G11C13/0002 , G11C13/003 , G11C2013/007120130101 , G11C2213/7920130101 , G11C2213/8220130101 , G11C13/0061 , G11C13/0069 , G11C13/0007
-
公开(公告)号：EP4412439A3
公开(公告)日：2024-09-11
申请号：EP24182923.3
申请日：2019-11-22
CPC分类号： G11C2213/3020130101 , G11C13/003 , G11C2213/7620130101 , G11C13/0004 , C03C3/321 , G11C11/2259 , G11C11/221 , H10B63/24 , H10B63/80 , H10N70/20 , H10N70/8825 , H10N70/231 , H10N70/8828 , H10N70/826
摘要： Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.
-
5.发明公开
公开(公告)号：EP4411737A1
公开(公告)日：2024-08-07
申请号：EP24154330.5
申请日：2024-01-29
发明人： BENHAMMADI, Jawad
CPC分类号： G11C16/22 , G11C7/24 , G11C13/0059 , G11C13/0064 , G11C16/3459 , G11C29/40 , G11C29/52 , G11C2029/440220130101
摘要： La présente description concerne un procédé de vérification d'une écriture d'une clé dans une mémoire non-volatile (104) comprenant les étapes suivantes: stocker dans un registre (206) d'une interface (106) de ladite mémoire, un premier code de redondance cyclique de ladite clé, précalculé ; écrire la clé de sécurité dans une zone (218) de la mémoire non-volatile (104); copier la clé de sécurité écrite dans ladite zone (218) vers un deuxième registre (212) de ladite interface (106); calculer un deuxième code de redondance cyclique sur un message formé par la clé de sécurité copiée à laquelle est adossé le premier code de redondance cyclique ; si le deuxième code de redondance cyclique est équivalent à la valeur nulle, considérer l'écriture de la clé de sécurité dans ladite mémoire non volatile (104) comme valide.
-
公开(公告)号：EP4399332A1
公开(公告)日：2024-07-17
申请号：EP22867963.5
申请日：2022-09-06
申请人： NAIO, Inc.
发明人： KOOL, Eric
IPC分类号： C12Q1/6869 , C12Q1/6806 , G11C13/00 , G11C11/56 , C07H21/04
CPC分类号： C12Q1/6806 , G11C13/0019
-
公开(公告)号：EP4390936A1
公开(公告)日：2024-06-26
申请号：EP23219178.3
申请日：2023-12-21
发明人： SABBIONE, Chiara , NAVARRO, Gabriele , TESSAIRE, Magali , FREI, Michel Ranjit , NISTOR, Lavinia-Elena
CPC分类号： H10N70/8828 , H10N70/231 , H10N70/041 , H10N70/826 , G11C13/0004 , H10N70/026 , H10N70/235
摘要： The invention relates to a material stack, a microelectronic device that integrates such stack and a method for obtaining such stack.
A non-limitative application of the invention relates to Phase-Change Memory device.
The material stack 10 for microelectronic device 1 comprises:
a. A substrate 11,
b. A first undoped crystalline layer 12 on the substrate, said undoped crystalline layer having a thickness superior to 4 nm, and
c. A Si-doped crystalline chalcogenide layer 13 on the undoped crystalline layer, said Si-doped crystalline chalcogenide layer being doped with less than 20 at.%, and preferably less than 12 at.%, of Si.
The provided material stack shows a satisfying stability contributing to retard the stack possible reorganization (i.e. intermixing) that could happen during the manufacturing of the material stack and during the subsequent manufacturing of said microelectronic device.-
公开(公告)号：EP4390933A1
公开(公告)日：2024-06-26
申请号：EP22315346.1
申请日：2022-12-21
发明人： Sabbione, Chiara , Navarro, Gabriele , Tessaire, Magali , Frei, Michel Ranjit , Nistor, Lavinia-Elena
CPC分类号： H10N70/8828 , H10N70/231 , H10N70/041 , H10N70/826 , G11C13/0004 , H10N70/026 , H10N70/235
摘要： The invention relates to a material stack, a microelectronic device that integrates such stack and a method for obtaining such stack.
A non-limitative application of the invention relates to Phase-Change Memory device. The material stack (10) for microelectronic device (1) comprises:
a. A substrate (11),
b. A first undoped crystalline layer (12) on the substrate, said undoped crystalline layer having a thickness superior to 4 nm, and
c. A Si-doped crystalline chalcogenide layer (13) on the undoped crystalline layer, said Si-doped crystalline chalcogenide layer being doped with less than 20 at.%, and preferably less than 12 at.%, of Si.
The provided material stack shows a satisfying stability contributing to retard the stack possible reorganization (i.e. intermixing) that could happen during the manufacturing of the material stack and during the subsequent manufacturing of said microelectronic device.-
公开(公告)号：EP4386756A1
公开(公告)日：2024-06-19
申请号：EP23215662.0
申请日：2023-12-11
发明人： CHOI, Yonghyuk , YU, Jaeduk , LEE, Yohan
IPC分类号： G11C16/34 , G11C16/04 , G11C29/52 , G11C29/44 , G11C5/06 , G11C11/56 , G11C13/00 , G11C16/26 , G11C16/32 , G11C29/12 , G11C29/02
CPC分类号： G11C16/3404 , G11C16/32 , G11C16/26 , G11C29/52 , G11C2029/120220130101 , G11C5/063 , G11C11/5642 , G11C16/0483 , G11C13/0033 , G11C29/025 , G11C29/4401
摘要： A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.
-
10.发明公开
公开(公告)号：EP4354436A1
公开(公告)日：2024-04-17
申请号：EP23187989.1
申请日：2023-07-27
CPC分类号： G11C7/1006 , G06F7/5443 , G06N3/065 , G11C11/54 , G11C11/56 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C7/1084 , G11C7/12 , G11C27/026 , G11C2213/7720130101 , G11C7/1039
摘要： A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.
-
-
-
-
-
-
-
-
-
搜索结果
1337 条记录 (耗时 0.023 秒)
