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    Method for increasing device reliability by selectively depopulating solder balls from foot print of ball grid array package
    21.
    发明专利
    Method for increasing device reliability by selectively depopulating solder balls from foot print of ball grid array package 审中-公开
    通过球形阵列包装的脚印打印可选择性地增加设备可靠性的方法

    公开(公告)号：JP2012069984A

    公开(公告)日：2012-04-05

    申请号：JP2011255225

    申请日：2011-11-22

    Applicant: Texas Instr Inc ,  テキサス インスツルメンツ インコーポレイテツド

    Inventor： LYNE KEVIN

    IPC: H01L23/12 ,  H05K3/00 ,  H01L23/498 ,  H05K1/11

    CPC classification number: H05K1/112 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H05K2201/09227 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a ball grid array (BGA) package that increases the routability of the package substrate and that increases device reliability.SOLUTION: A routing technique for improving device reliability by selectively depopulating solder balls (and their respective solder ball pads 34, vias 32 and traces or lines 30) from a conventional foot print of a ball grid array (BGA) package, and a BGA package so modified. The routing technique uses the gap resulting from the depopulated solder balls as additional space for routing traces or lines from solder ball pads to an exterior surface of a substrate upon which a semiconductor die is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls on the packages that continue shrinking, thereby increasing device reliability.

    Abstract translation: 要解决的问题：提供一种球栅阵列（BGA）封装，其增加了封装衬底的可布线性，并提高了器件的可靠性。 解决方案：一种用于通过选择性地将焊球（及其相应的焊球34，通孔32和迹线或线30）从球栅阵列（BGA）封装的常规脚印中放下而提高器件可靠性的布线技术，以及 一个BGA封装如此修改。 路由技术使用从人口稀少的焊球形成的间隙作为用于将迹线或线从焊球焊盘路由到其上安装有半导体管芯的衬底的外表面的附加空间。 本发明的优点在于，其允许保持最佳通孔直径，同时增加包装上继续收缩的焊球的数量，从而提高器件的可靠性。 版权所有（C）2012，JPO＆INPIT

    Wiring path determination method for wiring board, and wiring path determination method for semiconductor device
    22.
    发明专利
    Wiring path determination method for wiring board, and wiring path determination method for semiconductor device 审中-公开
    接线板布线路线测定方法及半导体器件接线路径测定方法

    公开(公告)号：JP2012063934A

    公开(公告)日：2012-03-29

    申请号：JP2010207073

    申请日：2010-09-15

    Applicant: Toshiba Corp ,  株式会社東芝

    Inventor： NAKANO MIKIO

    IPC: G06F17/50 ,  H01L21/82

    CPC classification number: H05K3/0005 ,  G06F17/5077 ,  H05K2201/09227 ,  Y10T29/49155 ,  Y10T29/49156

    Abstract: PROBLEM TO BE SOLVED: To provide a wiring method that improves wiring properties while reducing consumptions of a design time and computer resources.SOLUTION: A wiring path determination method includes steps of: tracing a first wiring forming lattice continuously from an origin to extend additional wiring up to one first selected intersection selected out of a plurality of first intersections; calculating a first via arrangeable region in which an additional via can be arranged on a first wiring layer and a second via arrangeable region in which an additional via can be arranged on a second wiring layer based upon positions of designed wiring and a designed via; arranging the additional via which has the first selected intersection included at any position in a region on a lower surface so that the lower surface is included in the first via arrangeable region and an upper surface is included in the second via arrangeable region; and tracing a second wiring forming lattice continuously from the additional via to extend the additional wiring up to an endpoint.

    Abstract translation: 要解决的问题：提供一种在减少设计时间和计算机资源的消耗的同时提高布线性能的布线方法。 解决方案：布线路径确定方法包括以下步骤：从原点连续地跟踪第一布线形成格架，以将附加布线延伸到从多个第一相交中选出的一个第一选择交叉点; 计算第一通孔布置区域，其中可以基于设计布线和设计的通孔的位置在第一布线层和第二通孔布置区域上布置附加通孔，其中可以在第二布线层上布置附加通孔; 将具有第一所选交叉点的附加物布置在下表面上的区域中的任何位置处，使得下表面包括在第一通孔布置区域中，并且上表面包括在第二通孔布置区域中; 并且从附加通道连续地跟踪第二布线形成网格以将附加布线延伸到端点。 版权所有（C）2012，JPO＆INPIT

    Multilayer wiring board and semiconductor device
    27.
    发明专利
    Multilayer wiring board and semiconductor device 有权
    多层接线板和半导体器件

    公开(公告)号：JP2009135375A

    公开(公告)日：2009-06-18

    申请号：JP2007312137

    申请日：2007-12-03

    Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

    Inventor： HORIUCHI MICHIO ,  TOKUTAKE YASUE ,  SUGANUMA SHIGEAKI ,  KOIZUMI NAOYUKI ,  KATAGIRI FUMIMASA

    IPC: H01L23/12 ,  H05K1/02 ,  H05K3/34

    CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674

    Abstract: PROBLEM TO BE SOLVED: To provide a multilayer wiring board for preventing a load from being applied to design by efficiently drawing out a wiring pattern from a pad arrangement region.
    SOLUTION: In the multilayer wiring board 30, the pad arrangement region, where a connection pad 12 to which a semiconductor element is flip-chip connected is disposed in a square grid shape, is provided on a substrate, and the multilayer wiring board 30 has a wiring pattern, where the other end is drawn out of the connection pad 12 to the outside of the pad arrangement region. A pad non-arrangement region is periodically provided along the outer periphery of the pad arrangement region. When the pitch of the connection pad 12, a connection pad diameter, the minimum spacing between the wiring patterns and that between the wiring pattern and the connection pad 12, the minimum wiring width of the wiring pattern, and the number of columns and the number of rows where the pad 12 is not disposed in the pad non-arrangement region are set to P, d, s, w, Ndl, and Ndr, respectively, the connection pad 12 and the wiring patterns are disposed in the arrangement meeting a formula of ((Ndl+1)P-d-s)/(w+s)≥2Ndr+Ndl.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 解决的问题：提供一种用于通过从衬垫布置区域有效地拉出布线图案来提供用于防止施加负载的多层布线板。 解决方案：在多层布线板30中，将衬底布置区域设置在基板上，其中将半导体元件倒装芯片连接的连接焊盘12设置为方格栅格，并且多层布线 板30具有布线图案，其中另一端从连接垫12拉出到垫布置区域的外部。 沿衬垫布置区域的外周周期性地设置衬垫非排列区域。 当连接焊盘12的间距，连接焊盘直径，布线图案与布线图案和连接焊盘12之间的最小间距，布线图案的最小布线宽度，列数和数量 其中焊盘12未设置在焊盘非排列区域中的行被分别设置为P，d，s，w，Nd1和Ndr，连接焊盘12和布线图案以满足公式 （（Nd1 + 1）Pds）/（w + s）≥2Ndr+ Nd1。 版权所有（C）2009，JPO＆INPIT

    Semiconductor device
    30.
    发明专利
    Semiconductor device 有权
    半导体器件

    公开(公告)号：JP2005340247A

    公开(公告)日：2005-12-08

    申请号：JP2004153086

    申请日：2004-05-24

    Applicant: Renesas Technology Corp ,  株式会社ルネサステクノロジ

    Inventor： YOSHIKAWA YASUHIRO ,  SUWA MOTOHIRO ,  NANBU HIROAKI

    IPC: H01L23/12 ,  H01L23/04 ,  H01L23/498 ,  H01L29/40 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11

    CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00012

    Abstract: PROBLEM TO BE SOLVED: To restrain crosstalk noise among the signals having the relation in which one signal becomes a synchronous signal of the other signal.
    SOLUTION: A wiring board (2) has a plurality of wiring layers (L1 to L4). On one surface, a plurality of chip connection electrodes (5) to be connected with the semiconductor chip (3) are provided, while on the other surface, a plurality of external connection electrodes (6) of the semiconductor device are provided. For coupling of connection electrodes and external connection electrodes corresponding with each other, wires formed on the wiring layer and via (7) for connecting wires between the wiring layers are provided. A plurality of chip connection electrodes include a first chip connection electrode for a first signal which is varied in its logical value, and a second chip connection electrode for a second signal which is varied after the variation timing of the first signal. A wiring layer mainly for wiring of the route from the first chip connection electrode up to a first external connection electrode corresponding thereto is formed, resulting in difference from the wiring layer mainly for wiring of the route from the second chip connection electrode provided adjacent to the first chip connection electrode up to a second external connection electrode corresponding thereto.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：为了抑制具有其中一个信号变成另一个信号的同步信号的关系的信号之间的串扰噪声。 电路板（2）具有多个布线层（L1〜L4）。 在一个表面上，设置与半导体芯片（3）连接的多个芯片连接电极（5），而在另一个表面上设置有半导体器件的多个外部连接电极（6）。 为了连接彼此对应的连接电极和外部连接电极，提供了形成在布线层上的布线和用于在布线层之间连接布线的通孔（7）。 多个芯片连接电极包括用于其逻辑值变化的第一信号的第一芯片连接电极和在第一信号的变化定时之后变化的第二信号的第二芯片连接电极。 形成主要用于从第一芯片连接电极到对应于其的第一外部连接电极的布线的布线层，导致与布线层的不同，布线层主要用于从邻近设置的第二芯片连接电极 第一芯片连接电极直到与其对应的第二外部连接电极。 版权所有（C）2006，JPO＆NCIPI

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