公开(公告)号：JP2003086690A

公开(公告)日：2003-03-20

申请号：JP2001267522

申请日：2001-09-04

申请人： MEGIC CORP

发明人： MUU-SHUN RIN

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

摘要： PROBLEM TO BE SOLVED: To provide a high performance system on-chip using a post passivation method. SOLUTION: Electric elements of high quality (e.g. inductor, capacitor or resistor) are formed on a passivation layer 18 or a surface of a thick polymer layer 20. A method further provides a method for mounting a discrete electronic element in the state that the element is isolated from a surface of a lower silicon substrate 10 to some extent.

公开(公告)号：JP2007005808A

公开(公告)日：2007-01-11

申请号：JP2006173769

申请日：2006-06-23

申请人： Megic Corp ,  米輯電子股▲分▼有限公司

发明人： HAYASHI SHIGEO ,  CHOU CHIEN-KANG ,  CHEN KE-HUNG

IPC分类号： H01L21/3205 ,  H01L23/12 ,  H01L23/52

CPC分类号： H01L23/5227 ,  H01L21/2885 ,  H01L21/563 ,  H01L21/76801 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/5223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05183 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/45183 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/83851 ,  H01L2224/05552 ,  H01L2224/05599

摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a line device which is to be miniaturized. SOLUTION: A first metal pole and a second metal pole are arranged on a substrate. When maximum width of the first metal pole is divided by height of the first metal pole and the second metal pole, it is smaller than "4". Height of the first metal pole is 20 μm to 300 μm, and a distance from a center point of the first metal pole to a center point of the second metal pole is 10 μm to 250 μm. Thus, the distance between the metal poles can be reduced to ≤250 μm, and the number of pin holes can be suppressed to a target being ≤400. Performance of IC can effectively be improved, and resistance and load of an IC metal connection line of a low power IC element can be sharply reduced. COPYRIGHT: (C)2007,JPO&INPIT

摘要翻译： 要解决的问题：提供一种要小型化的线路装置的制造方法。 解决方案：第一金属极和第二金属极布置在基板上。 当第一金属极的最大宽度除以第一金属极和第二金属极的高度时，其小于“4”。 第一金属极的高度为20μm〜300μm，从第一金属极的中心点到第二金属极的中心点的距离为10μm〜250μm。 因此，金属极之间的距离可以降低到≤250μm，并且可以将针孔的数量抑制到目标值≤400。 可以有效地提高IC的性能，并且能够大幅降低低功率IC元件的IC金属连接线的电阻和负载。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2010239137A

公开(公告)日：2010-10-21

申请号：JP2010097554

申请日：2010-04-21

申请人： Megic Corp ,  メジカ・コーポレーション

发明人： MUU-SHUN RIN

IPC分类号： H01L21/822 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/04

CPC分类号： H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

摘要： PROBLEM TO BE SOLVED: To provide a multiple integrated circuit chip structure for performing inter-chip communication between integrated circuit chips having a structure including neither an ESD protection circuit nor an input/output circuit.
SOLUTION: The multiple integrated circuit chip structure includes an ESD protection circuit 387 for communicating with an external test system during a test and a burn-in procedure, and an inter-chip interface circuit 360 configured to selectively connect an internal circuit of an integrated circuit so as to test an interface circuit 385 having an input/output circuit 389. The multiple integrated circuit chip structure has a first integrated circuit chip 305 fitted to one or more second integrated circuit chips 310 so as to physically and electrically connect an integrated circuit chip.
COPYRIGHT: (C)2011,JPO&INPIT

摘要翻译： 要解决的问题：提供一种用于在具有既不包括ESD保护电路也不包括输入/​​输出电路的结构的集成电路芯片之间进行芯片间通信的多集成电路芯片结构。 解决方案：多集成电路芯片结构包括用于在测试和老化过程期间与外部测试系统通信的ESD保护电路387，以及芯片间接口电路360，其被配置为选择性地连接内部电路 集成电路，以便测试具有输入/输出电路389的接口电路385.多重集成电路芯片结构具有装配到一个或多个第二集成电路芯片310上的第一集成电路芯片305，以物理和电连接 集成电路芯片。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2003258014A

公开(公告)日：2003-09-12

申请号：JP2002056997

申请日：2002-03-04

申请人： MEGIC CORP

发明人： JIN-YUAN LEE ,  MUU SHUN RIN ,  CHIN-CHEN FAN

IPC分类号： H01L21/60

摘要： PROBLEM TO BE SOLVED: To provide a method for forming a metal bump on a semiconductor surface. SOLUTION: A barrier layer is deposited over a layer of passivation including an opening to a contact pad formed in the layer of passivation. A column formed of three metal layers is formed by overlying the barrier layer and aligned with contact pad and having a diameter, that is about equal to the surface of the contact pad. The three metal layers of the column comprises, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation, and thereafter the reflow of the solder metal is performed, thus completing the formation of the solder bump. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2007005810A

公开(公告)日：2007-01-11

申请号：JP2006173778

申请日：2006-06-23

申请人： Megic Corp ,  米輯電子股▲分▼有限公司

发明人： HAYASHI SHIGEO ,  CHOU CHIEN-KANG ,  CHEN KE-HUNG

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/12 ,  H01L23/52 ,  H01L27/04

CPC分类号： H01L23/5227 ,  H01L21/2885 ,  H01L21/563 ,  H01L21/76801 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/5223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05183 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/45183 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/83851 ,  H01L2224/05552 ,  H01L2224/05599

摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a line device, which relieves stress and makes an interval distance of a contact window structure small. SOLUTION: A semiconductor base part 30 includes at least one first metal pole positioned on the semiconductor base part 30 and one first polymer layer 46 positioned on the semiconductor base part 30 and on the first metal pole, The first polymer layer 46 is removed until one top part of the metal pole is exposed. One second metal pole is supplied. One metal connection line layer is formed on the first polymer layer 46 by an electroplating system. The metal connection line layer is connected to the first metal pole and the second metal pole. One titanium content metal layer is formed on the first polymer layer 46 before a forming step of the metal connection line layer. COPYRIGHT: (C)2007,JPO&INPIT

摘要翻译： 要解决的问题：提供减轻应力并使接触窗结构的间隔距离变小的线路装置的制造方法。 解决方案：半导体基底部分30包括位于半导体基底部分30上的至少一个第一金属极和位于半导体基底部分30上和第一金属极上的一个第一聚合物层46.第一聚合物层46是 去除直到金属极的一个顶部暴露。 提供一个第二个金属极。 通过电镀系统在第一聚合物层46上形成一个金属连接线层。 金属连接线层连接到第一金属极和第二金属极。 在金属连接线层的形成步骤之前，在第一聚合物层46上形成一个钛含量金属层。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007005809A

公开(公告)日：2007-01-11

申请号：JP2006173775

申请日：2006-06-23

申请人： Megic Corp ,  米輯電子股▲分▼有限公司

发明人： HAYASHI SHIGEO ,  CHOU CHIEN-KANG ,  CHEN KE-HUNG

IPC分类号： H01L21/3205 ,  H01L21/60 ,  H01L23/12 ,  H01L23/52

CPC分类号： H01L23/5227 ,  H01L21/2885 ,  H01L21/563 ,  H01L21/76801 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/5223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05183 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/45183 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/83851 ,  H01L2224/05552 ,  H01L2224/05599

摘要： PROBLEM TO BE SOLVED: To provide a manufacturing process of a line device structure, which relieves stress and makes an interval distance of a contact window structure small, and to provide the structure. SOLUTION: The line device structure includes a substrate, a first metal pole 68 and a second metal pole. The first metal pole 68 is positioned on the substrate. When a maximum side dimension Hw of the first metal pole 68 is divided by height Ht of the first metal pole 68, it is smaller than "4". Height of the first metal pole 68 is 20 μm to 300 μm. The second metal pole is positioned on the substrate. When a maximum side dimension of the second metal pole is divided by height of the second metal pole, it is smaller than "4". A distance Hb from a center point of the first metal pole to a center point of the second metal pole is 10 μm to 250 μm. COPYRIGHT: (C)2007,JPO&INPIT

摘要翻译： 要解决的问题：提供减轻应力并使接触窗结构的间隔距离较小的线路装置结构的制造工艺，并提供结构。 线路器件结构包括衬底，第一金属极68和第二金属极。 第一金属杆68位于基底上。 当第一金属杆68的最大侧面尺寸Hw除以第一金属杆68的高度Ht时，其小于“4”。 第一金属杆68的高度为20μm〜300μm。 第二金属杆位于基板上。 当第二金属极的最大侧面尺寸除以第二金属杆的高度时，其小于“4”。 从第一金属极的中心点到第二金属极的中心点的距离Hb为10μm〜250μm。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006332694A

公开(公告)日：2006-12-07

申请号：JP2006200592

申请日：2006-07-24

申请人： Megic Corp ,  メジカ・コーポレーション

发明人： JIN-YUAN LEE ,  MUU SHUN RIN ,  CHIN-CHEN FAN

IPC分类号： H01L21/60

CPC分类号： H01L2224/11 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012

摘要： PROBLEM TO BE SOLVED: To provide a method for forming metal bumps on a semiconductor surface. SOLUTION: A barrier layer is deposited over a passivation layer, containing an opening to a conductor pad formed in the passivation layer. A column formed of three metal layers is formed by overlying the barrier layer and aligned with the conductor pad and having a diameter, that is about equal on the surface of the conductor pad. The three metal layers of the column comprises, in succession, when proceeding from the layer that is in contact with the barrier layer, a layer of pillar-shaped metal, a layer of under-bump metal and a layer of solder metal. The layer of pillar-shaped metal is reduced in diameter, the barrier layer is removed selectively from the surface of the passivation layer, and thereafter, the reflow of the solder metal is performed, thus completing the formation of the solder bump. COPYRIGHT: (C)2007,JPO&INPIT

摘要翻译： 要解决的问题：提供一种在半导体表面上形成金属凸块的方法。 解决方案：阻挡层沉积在钝化层上，该钝化层包含形成在钝化层中的导体焊盘的开口。 由三个金属层形成的列通过覆盖阻挡层并与导体焊盘对准并且具有在导体焊盘的表面上大致相等的直径形成。 当从与阻挡层接触的层，柱状金属层，凸块下金属层和焊料金属层进行时，柱的三个金属层依次包括。 柱状金属层的直径减小，从钝化层的表面选择性地去除阻挡层，之后进行焊料金属的回流，从而完成焊料凸点的形成。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003332440A

公开(公告)日：2003-11-21

申请号：JP2002131172

申请日：2002-05-07

申请人： Megic Corp ,  メジック・コーポレーション

发明人： MUU-SHUN RIN

IPC分类号： H01L25/18 ,  H01L21/822 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L27/04

CPC分类号： H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/09701 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00014

摘要： PROBLEM TO BE SOLVED: To provide a chip structure for a multiply integrated circuit which performs chip-to-chip communication in terms of the chips for an integrated circuit having a structure without an ESD protection circuit and an input/output circuit.
SOLUTION: The chip structure for a multiply integrated circuit is provided with chip-to-chip interface circuits for selective connection of internal circuits in an integrated circuit for testing an interface circuit having the ESD protection circuit and the input/output circuit for establishing communication with an external testing system during a test and a burn-in process. The chip structure is also provided with a first integrated circuit chip which is attached to one or more second integrated circuit chips, so that the integrated circuit chips are physically and electrically connected with each other.
COPYRIGHT: (C)2004,JPO

摘要翻译： 要解决的问题：提供一种用于对具有没有ESD保护电路和输入/输出电路的结构的集成电路的芯片进行芯片到芯片通信的多集成电路的芯片结构。 解决方案：多集成电路的芯片结构设置有芯片到芯片接口电路，用于选择性地连接集成电路中的内部电路，用于测试具有ESD保护电路和输入/输出电路的接口电路 在测试和老化过程中建立与外部测试系统的通信。 芯片结构还具有附接到一个或多个第二集成电路芯片的第一集成电路芯片，使得集成电路芯片彼此物理和电连接。 版权所有（C）2004，JPO

公开(公告)号：JP2002270686A

公开(公告)日：2002-09-20

申请号：JP2001056759

申请日：2001-03-01

申请人： MEGIC CORP

发明人： M S RIN

IPC分类号： H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04

摘要： PROBLEM TO BE SOLVED: To provide a new method to forming an interconnection line. SOLUTION: A thin line interconnection part (60) is provided in the surface of a substrate (10), or in a first dielectrics layer (12), located above a semiconductor circuit (42) formed over it. A passivation layer (18) sticks to the dielectrics layer, while a second thick dielectrics layer (20) is formed on the surface of the passivation layer. A thick and wide interconnection line is formed in the second thick dielectrics layer. The first dielectrics layer may be so omitted, to form a wide and thick interconnection network on the surface of the passivation layer which sticks to the surface of substrate.

公开(公告)号：JP2002246547A

公开(公告)日：2002-08-30

申请号：JP2001028283

申请日：2001-02-05

申请人： MEGIC CORP

发明人： LIN MOU SHIUNG

IPC分类号： H01L21/822 ,  H01L27/04

摘要： PROBLEM TO BE SOLVED: To provide a method of forming an inductor for a high-performance integrated circuit overlaid on a surface of a semiconductor substrate. SOLUTION: An electric element (for example, inductor, capacitor, or resistor) is additionally formed on a passivation layer or a thick polymer layer. A method for mounting a discrete electric element in a separated state from the lower surface of the silicon substrate is provided.