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1.发明授权公开(公告)号：US08115272B2
公开(公告)日：2012-02-14
申请号：US13208098
申请日：2011-08-11
IPC分类号： H01L21/70
CPC分类号： H01L28/40 , H01L21/764 , H01L27/08 , H01L28/10 , H01L28/20 , H01L31/101
摘要： An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.
摘要翻译： 一种装置包括其中具有空腔（4）的半导体层（2）。 在半导体层上形成介电层（3）。 多个蚀刻剂开口（24）延伸穿过介电层，用于通过蚀刻剂以蚀刻空腔。 SiO 2柱（25）从空腔的底部延伸以接合并支撑在腔上延伸的介电层的一部分。 在一个实施例中，电介质层上的覆盖层（34）覆盖蚀刻剂开口。
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2.发明授权Method for manufacturing improved sidewall structures for use in semiconductor devices 有权用于制造用于半导体器件的改进的侧壁结构的方法公开(公告)号：US07018888B2
公开(公告)日：2006-03-28
申请号：US10902902
申请日：2004-07-30
IPC分类号： H01L21/8238
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (100), among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having sidewall spacers (210 or 410) on opposing sidewalls thereof and placing source/drain implants (310, 510) into the substrate (110) proximate the gate structure (130). The method further includes removing at least a portion of the sidewall spacers (210 or 410) and annealing the source/drain implants (310, 510) to form source/drain regions (710) after removing the at least a portion of the sidewall spacers (210 or 410).
摘要翻译： 本发明提供一种制造半导体器件的方法和用于制造包括该半导体器件的集成电路的方法。 除了其他步骤之外，制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（130），所述栅极结构（130）在其相对的侧壁上具有侧壁间隔物（210或410） 源极/漏极注入（310,510）到靠近栅极结构（130）的衬底（110）中。 所述方法还包括：移除所述侧壁间隔物（210或410）的至少一部分并且在去除所述侧壁间隔物的所述至少一部分之后对所述源/漏植入物（310,510）进行退火以形成源极/漏极区域（710） （210或410）。
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公开(公告)号：US20120108076A1
公开(公告)日：2012-05-03
申请号：US13346603
申请日：2012-01-09
申请人： Brian E. Goodlin , Qidu Jiang
发明人： Brian E. Goodlin , Qidu Jiang
IPC分类号： H01L21/30
CPC分类号： H01L21/02104 , C23C16/45565 , C23C16/45574 , H01L21/02197 , Y10T137/0318
摘要： A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.
摘要翻译： 一种CVD淋浴头，其包括圆形的内部喷淋头和至少一个外部环形喷头。 至少两个处理气体输送管连接到每个喷头。 另外，一个双喷头，其包括圆形的内部喷淋头和至少一个外部环形喷头，其中每个喷头与氧加上铅，锆和钛有机金属的气体混合物。 一种在晶片上沉积CVD薄膜的方法。 另外，在晶片上沉积PZT薄膜的方法。
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4.发明授权公开(公告)号：US07833895B2
公开(公告)日：2010-11-16
申请号：US12463282
申请日：2009-05-08
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.
摘要翻译： 一种用于制造IC的方法，包括从第一至第
一通孔（TSV）和IC及其电子组件。 提供具有包括顶部半导体表面和底部表面的衬底厚度的衬底，其包括至少一个嵌入式TSV，其包括形成在电介质衬垫上的介电衬垫和导电填充材料。 基板的底表面的一部分被机械地移除以接近但不到达嵌入的TSV尖端。 在机械去除之后，具有保护层厚度的保护基层保留在嵌入TSV的尖端上。 用于去除保护基底层的机械蚀刻除外的化学蚀刻用于形成整体的TSV尖端，其具有通常从基底的底表面突出的暴露尖端部分。 化学蚀刻通常是三步化学蚀刻。-
公开(公告)号：US10526198B2
公开(公告)日：2020-01-07
申请号：US13411849
申请日：2012-03-05
IPC分类号： B81B7/00 , H01L27/144 , B81C1/00
摘要： A MEMS IR sensor, with a cavity in a substrate underlapping an overlying layer and a temperature sensing component disposed in the overlying layer over the cavity, may be formed by forming an IR-absorbing sealing layer on the overlying layer so as to cover access holes to the cavity. The sealing layer is may include a photosensitive material, and the sealing layer may be patterned using a photolithographic process to form an IR-absorbing seal. Alternately, the sealing layer may be patterned using a mask and etch process to form the IR-absorbing seal.
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6.发明申请公开(公告)号：US20100327393A1
公开(公告)日：2010-12-30
申请号：US12456910
申请日：2009-06-24
IPC分类号： H01L29/66 , H01L21/306 , H01L23/00
CPC分类号： G01J5/12 , B81B2201/0292 , B81C1/00047 , G01J5/02 , G01J5/0225 , G01J5/024
摘要： A semiconductor device includes a semiconductor layer (2) and a dielectric stack (3) on the semiconductor layer. A plurality of etchant openings (24-1,2 . . . ) are formed through the dielectric stack (3) for passage of etchant for etching a plurality of overlapping sub-cavities (4-1,2 . . . ), respectively. The etchant is introduced through the etchant openings to etch a composite cavity (4) in the semiconductor layer by simultaneously etching the plurality of overlapping sub-cavities into the semiconductor layer.
摘要翻译： 半导体器件包括在半导体层上的半导体层（2）和电介质叠层（3）。 多个蚀刻剂开口（24-1,2 ...）通过电介质叠层（3）形成，用于通过蚀刻剂，分别蚀刻多个重叠的子腔（4-1,2 ...）。 通过蚀刻剂开口引入蚀刻剂，以通过同时将多个重叠子腔同时蚀刻到半导体层中来蚀刻半导体层中的复合空腔（4）。
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公开(公告)号：US20090289324A1
公开(公告)日：2009-11-26
申请号：US12467019
申请日：2009-05-15
IPC分类号： H01L29/06 , H01L21/02 , H01L21/768 , H01L21/762 , H01L23/48
CPC分类号： H01L29/945 , H01L21/308 , H01L21/31111 , H01L21/31116 , H01L21/76229 , H01L21/76898 , H01L27/1087 , H01L29/66181 , Y10S438/978
摘要： A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature.
摘要翻译： 一种形成IC器件的方法包括提供衬底并形成图案化掩模层，其包括至少一个具有至少一个掩模层的掩模区域和由掩模层限定的特征区域。 蚀刻在衬底中形成蚀刻特征，其中蚀刻期间的底切形成相对于掩模层的外边缘凹陷的蚀刻特征的表面部分上的至少一个掩模悬垂区域。 除了任何额外的图案化步骤之外的回拉蚀刻工艺横向蚀刻掩模层。 拉回蚀刻的条件保留掩模层的至少一部分并且将掩模悬伸部分的长度减小至少50％，或者完全消除掩模悬垂区域。 然后在拉回蚀刻工艺之后填充蚀刻的特征以形成填充的蚀刻特征。
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公开(公告)号：US20130249096A1
公开(公告)日：2013-09-26
申请号：US13591026
申请日：2012-08-21
申请人： Mona Eissa , Nicholas S. Dellas , Brian E. Goodlin
发明人： Mona Eissa , Nicholas S. Dellas , Brian E. Goodlin
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/53238 , H01L25/0657 , H01L25/074 , H01L2224/13025 , H01L2224/131 , H01L2224/16146 , H01L2924/1461 , H01L2924/014 , H01L2924/00
摘要： A method for forming a through silicon via (TSV) in a substrate comprising: depositing a seed layer in a TSV hole; and annealing the seed layer.
摘要翻译： 一种在衬底中形成贯穿硅通孔（TSV）的方法，包括：在TSV孔中沉积晶种层; 并退火晶种层。
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9.发明申请公开(公告)号：US20110294246A1
公开(公告)日：2011-12-01
申请号：US13208130
申请日：2011-08-11
IPC分类号： H01L21/768 , H01L21/02
CPC分类号： H01L28/40 , H01L21/764 , H01L27/08 , H01L28/10 , H01L28/20 , H01L31/101
摘要： An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.
摘要翻译： 一种装置包括其中具有空腔（4）的半导体层（2）。 在半导体层上形成介电层（3）。 多个蚀刻剂开口（24）延伸穿过介电层，用于通过蚀刻剂以蚀刻空腔。 SiO 2柱（25）从空腔的底部延伸以接合并支撑在腔上延伸的介电层的一部分。 在一个实施例中，电介质层上的覆盖层（34）覆盖蚀刻剂开口。
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公开(公告)号：US20110291222A1
公开(公告)日：2011-12-01
申请号：US13208098
申请日：2011-08-11
CPC分类号： H01L28/40 , H01L21/764 , H01L27/08 , H01L28/10 , H01L28/20 , H01L31/101
摘要： An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.
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