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    Semiconductor package
    1.
    发明授权
    Semiconductor package 有权
    半导体封装

    公开(公告)号：US07737538B2

    公开(公告)日：2010-06-15

    申请号：US11979809

    申请日：2007-11-08

    Applicant: Chao-Chen Chen ,  Lin-Gi Yang ,  Chia-Chi Chou ,  Shih-Chieh Teng

    Inventor： Chao-Chen Chen ,  Lin-Gi Yang ,  Chia-Chi Chou ,  Shih-Chieh Teng

    IPC: H01L23/495 ,  H01L21/00

    CPC classification number: H01L27/14618 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor package. The semiconductor package of the invention comprises: a substrate comprising at least one exposed area with photosensitive devices; a cover for isolating the exposed area from the external atmosphere, wherein one of either the substrate or the cover is a base, and the other is a top structure; and a dam formed on the base to form a cavity, wherein the top of the dam has a recess, the dam is attached the top structure by an adhesive, and the cavity corresponds to the exposed area.

    Abstract translation: 半导体封装。 本发明的半导体封装包括：包含至少一个具有光敏器件的暴露区域的衬底; 用于将暴露区域与外部空气隔离的盖子，其中所述基板或所述盖板中的一个是基座，而另一个是顶部结构; 和形成在基座上以形成空腔的坝，其中坝的顶部具有凹部，坝通过粘合剂附接到顶部结构，并且空腔对应于暴露的区域。

    Semiconductor package
    2.
    发明申请
    Semiconductor package 有权
    半导体封装

    公开(公告)号：US20090121303A1

    公开(公告)日：2009-05-14

    申请号：US11979809

    申请日：2007-11-08

    Applicant: Chao-Chen Chen ,  Lin-Gi Yang ,  Chia-Chi Chou ,  Shih-Chieh Teng

    Inventor： Chao-Chen Chen ,  Lin-Gi Yang ,  Chia-Chi Chou ,  Shih-Chieh Teng

    IPC: H01L31/0203 ,  H01L31/18

    CPC classification number: H01L27/14618 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor package. The semiconductor package of the invention comprises: a substrate comprising at least one exposed area with photosensitive devices; a cover for isolating the exposed area from the external atmosphere, wherein one of either the substrate or the cover is a base, and the other is a top structure; and a dam formed on the base to form a cavity, wherein the top of the dam has a recess, the dam is attached the top structure by an adhesive, and the cavity corresponds to the exposed area.

    Abstract translation: 半导体封装。 本发明的半导体封装包括：包含至少一个具有光敏器件的暴露区域的衬底; 用于将暴露区域与外部空气隔离的盖子，其中所述基板或所述盖板中的一个是基座，而另一个是顶部结构; 和形成在基座上以形成空腔的坝，其中坝的顶部具有凹部，坝通过粘合剂附接到顶部结构，并且空腔对应于暴露的区域。

    Integrated process for fuse opening and passivation process for Cu/Low-K IMD
    3.
    发明申请
    Integrated process for fuse opening and passivation process for Cu/Low-K IMD 审中-公开
    Cu / Low-K IMD的保险丝开路和钝化工艺的综合工艺

    公开(公告)号：US20050218476A1

    公开(公告)日：2005-10-06

    申请号：US11132086

    申请日：2005-05-18

    Applicant: Tze-Liang Lee ,  Chao-Chen Chen

    Inventor： Tze-Liang Lee ,  Chao-Chen Chen

    IPC: H01L21/44 ,  H01L23/48 ,  H01L23/525

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A new process flow is provided for the creation of a fuse contact and a bond pad. The invention starts with a semiconductor substrate over the surface of which is provided top level metal and fuse metal in the surface of a layer of insulation deposited over the surface of the substrate. A first etch stop layer is deposited over the surface of the layer of insulation over which a first passivation layer is deposited, an opening is created through these layers exposing the top level metal. A metal plug is created overlying the exposed surface of the top level metal. A stack of a patterned and etched hard mask layers, having been deposited at part of the creation of the metal plug and overlying a layer of metal plug material, remains in place over the surface of the created metal plug. A second layer of passivation material is deposited, the second layer of passivation is patterned and etched exposing the surface of the first layer of passivation overlying the fuse metal and exposing the surface of the stack of hard mask layers overlying the created metal plug. The stack of hard mask layers is then removed from the surface of the metal plug, exposing the surface of the metal plug to serve as a contact pad and further reducing the thickness of the first layer of passivation over the surface of the fuse metal, making the fuse more accessible for fuse blowing.

    Abstract translation: 提供了一种新的工艺流程来创建保险丝触点和接合垫。 本发明从其表面上提供顶层金属和熔丝金属的半导体衬底开始沉积在衬底表面上的绝缘层表面。 第一蚀刻停止层沉积在绝缘层的表面上，在绝缘层的表面上沉积第一钝化层，通过暴露顶层金属的这些层产生开口。 在顶层金属的暴露表面上形成一个金属塞。 已经沉积在金属插塞的一部分并且覆盖一层金属插塞材料的图案和蚀刻的硬掩模层的堆叠保持在所产生的金属插塞的表面上的适当位置。 沉积第二层钝化材料，第二层钝化被图案化和蚀刻，暴露第一层钝化层的表面，覆盖熔丝金属并暴露覆盖所产生的金属插塞的硬掩模层堆叠的表面。 然后从金属塞的表面去除堆叠的硬掩模层，暴露金属塞的表面以用作接触焊盘，并进一步减小熔丝金属表面上的第一钝化层的厚度，使得 保险丝更容易熔断。

    CU second electrode process with in situ ashing and oxidation process
    4.
    发明授权
    CU second electrode process with in situ ashing and oxidation process 有权
    CU第二电极工艺与原位灰化和氧化工艺

    公开(公告)号：US06458650B1

    公开(公告)日：2002-10-01

    申请号：US09908821

    申请日：2001-07-20

    Applicant: Yi-Chen Huang ,  Li-Chih Chao ,  Chao-Chen Chen

    Inventor： Yi-Chen Huang ,  Li-Chih Chao ,  Chao-Chen Chen

    IPC: H01L218242

    CPC classification number: H01L28/91 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76802 ,  H01L21/76814

    Abstract: A new method is provided for the creation of an opening over which the second electrode of a MIM capacitor is to be deposited. The first electrode of the MIM is created in a first layer of Fluorine doped Silicon dioxide (SiO2) Glass (FSG) . A layer of insulation comprising silicon nitride is deposited over the surface of the first electrode. A second layer of Fluorine doped Silicon dioxide (SiO2) Glass (FSG) is deposited over the surface of the layer of silicon nitride, an etch stop layer of silicon nitride is deposited over the surface of the second layer of FSG. The layers of etch stop and the second layer of FSG are patterned and etched using a dry etch, stopping on the layer-of insulation and exposing the surface of the layer of insulation. Next-and of critical importance to the invention is a step of photoresist ashing and oxidation of the surface of the layer of silicon nitride. The layer of photoresist can now be removed while concurrently, using a wet strip, the layer of silicon nitride oxidation is removed from the surface of the layer of silicon nitride. The process of creating a MIM capacitor can then proceed by creating the second electrode of the MIM capacitor.

    Abstract translation: 提供了一种新的方法，用于创建MIM电容器的第二电极将要沉积的开口。 MIM的第一电极在氟掺杂二氧化硅（SiO 2）玻璃（FSG）的第一层中产生。 包含氮化硅的绝缘层沉积在第一电极的表面上。 氟化二氧化硅（SiO 2）玻璃（FSG）的第二层沉积在氮化硅层的表面上，氮化硅的蚀刻停止层沉积在第二层FSG的表面上。 蚀刻停止层和FSG的第二层被图案化和蚀刻使用干蚀刻，停止在绝缘层上并暴露绝缘层的表面。 接下来对于本发明至关重要的是对氮化硅层的表面的光致抗蚀剂灰化和氧化的步骤。 现在可以同时去除光致抗蚀剂层，使用湿条，从氮化硅层的表面去除氮化硅层的氧化层。 然后可以通过产生MIM电容器的第二电极来进行制造MIM电容器的过程。

    SPRAY COATING SYSTEM
    5.
    发明申请
    SPRAY COATING SYSTEM 审中-公开
    喷涂系统

    公开(公告)号：US20110117283A1

    公开(公告)日：2011-05-19

    申请号：US12618464

    申请日：2009-11-13

    Applicant: Chia-Hao HSUEH ,  Yuan-Chun CHAO ,  Kuo-Hsing TENG ,  Chao-Chen CHEN

    Inventor： Chia-Hao HSUEH ,  Yuan-Chun CHAO ,  Kuo-Hsing TENG ,  Chao-Chen CHEN

    IPC: B05D1/02 ,  B05C9/08

    CPC classification number: H01L21/6715

    Abstract: A spray coating system is provided. The spray coating system includes a spin support for supporting and spinning the substrate; a sprayer for applying a material to an upper surface of the substrate; a cup surrounding a lateral and lower region of the spin support, wherein an opening is located in an upper central region of the cup; an air supply mechanism for supplying air flows to a back surface of the substrate to prevent the material from adhering thereto, and an exhaust zone disposed below a slanted surface of the cup for exhausting the air flow and material.

    Abstract translation: 提供喷涂系统。 喷涂系统包括用于支撑和旋转衬底的自旋支撑件; 用于将材料施加到所述基板的上表面的喷雾器; 围绕所述自旋支撑件的横向和下部区域的杯，其中开口位于所述杯的上中心区域中; 空气供给机构，用于向基板的后表面供给空气，以防止材料粘附到其上;排气区，设置在杯的倾斜表面下方排出气流和材料。

    Integrated process for fuse opening and passivation process for CU/LOW-K IMD
    7.
    发明授权
    Integrated process for fuse opening and passivation process for CU/LOW-K IMD 失效
    用于CU / LOW-K IMD的保险丝开路和钝化处理的集成过程

    公开(公告)号：US06911386B1

    公开(公告)日：2005-06-28

    申请号：US10176943

    申请日：2002-06-21

    Applicant: Tze-Liang Lee ,  Chao-Chen Chen

    Inventor： Tze-Liang Lee ,  Chao-Chen Chen

    IPC: H01L21/44 ,  H01L23/48 ,  H01L23/525

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A new process flow is provided for the creation of a fuse contact and a bond pad. The invention starts with a semiconductor substrate over the surface of which is provided top level metal and fuse metal in the surface of a layer of insulation deposited over the surface of the substrate. A first etch stop layer is deposited over the surface of the layer of insulation over which a first passivation layer is deposited, an opening is created through these layers exposing the top level metal. A metal plug is created overlying the exposed surface of the top level metal. A stack of a patterned and etched hard mask layers, having been deposited at part of the creation of the metal plug and overlying a layer of metal plug material, remains in place over the surface of the created metal plug. A second layer of passivation material is deposited, the second layer of passivation is patterned and etched exposing the surface of the first layer of passivation overlying the fuse metal and exposing the surface of the stack of hard mask layers overlying the created metal plug. The stack of hard mask layers is then removed from the surface of the metal plug, exposing the surface of the metal plug to serve as a contact pad and further reducing the thickness of the first layer of passivation over the surface of the fuse metal, making the fuse more accessible for fuse blowing.

    Abstract translation: 提供了一种新的工艺流程来创建保险丝触点和接合垫。 本发明从其表面上提供顶层金属和熔丝金属的半导体衬底开始沉积在衬底表面上的绝缘层表面。 第一蚀刻停止层沉积在绝缘层的表面上，在绝缘层的表面上沉积第一钝化层，通过暴露顶层金属的这些层产生开口。 在顶层金属的暴露表面上形成一个金属塞。 已经沉积在金属插塞的一部分并且覆盖一层金属插塞材料的图案和蚀刻的硬掩模层的堆叠保持在所产生的金属插塞的表面上的适当位置。 沉积第二层钝化材料，第二层钝化被图案化和蚀刻，暴露第一层钝化层的表面，覆盖熔丝金属并暴露覆盖所产生的金属插塞的硬掩模层堆叠的表面。 然后从金属塞的表面去除堆叠的硬掩模层，暴露金属塞的表面以用作接触焊盘，并进一步减小熔丝金属表面上的第一钝化层的厚度，使得 保险丝更容易熔断。

    Color filter and fabrication method thereof
    9.
    发明申请
    Color filter and fabrication method thereof 审中-公开
    滤色器及其制造方法

    公开(公告)号：US20090104545A1

    公开(公告)日：2009-04-23

    申请号：US11976169

    申请日：2007-10-22

    Applicant: Chao-Chen Chen ,  Joseph Lai ,  Cheng-Hong Yeh

    Inventor： Chao-Chen Chen ,  Joseph Lai ,  Cheng-Hong Yeh

    IPC: G03F1/00

    CPC classification number: G02B5/201 ,  G02B5/223 ,  G02F1/133516 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14685

    Abstract: Embodiments disclose a method for fabricating a color filter, comprising: providing a substrate; forming a planarization layer on the substrate; forming a first color layer over the planarization layer; exposing and developing the first color layer to form a patterned first color filter unit over the planarization layer; forming a second color layer over the planarization layer and the patterned first color filter unit; exposing and developing the second color layer to form a patterned second color filter unit over the planarization layer; forming a third color layer over the planarization layer and the patterned first and second color filter units; and etching back or chemical mechanical polishing (CMP) the third color layer to form a patterned third color filter unit over the planarization layer.

    Abstract translation: 实施例公开了一种制造滤色器的方法，包括：提供基板; 在所述基板上形成平坦化层; 在所述平坦化层上形成第一颜色层; 曝光和显影第一颜色层，以在平坦化层上形成图案化的第一滤色器单元; 在平坦化层和图案化的第一滤色器单元上形成第二颜色层; 曝光和显影第二颜色层以在平坦化层上形成图案化的第二滤色器单元; 在平坦化层和图案化的第一和第二滤色器单元上形成第三颜色层; 并对第三颜色层进行回蚀刻或化学机械抛光（CMP）以在平坦化层上形成图案化的第三滤色器单元。

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