利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

15 条记录 (耗时 0.016 秒)

    Fully silicided metal gate semiconductor device structure
    1.
    发明授权
    Fully silicided metal gate semiconductor device structure 有权
    全硅化金属栅半导体器件结构

    公开(公告)号：US07473975B2

    公开(公告)日：2009-01-06

    申请号：US11840774

    申请日：2007-08-17

    申请人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

    发明人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

    IPC分类号： H01L29/76

    CPC分类号： H01L29/6656 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/51 ,  H01L29/66545

    摘要： A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.

    摘要翻译： 一种形成半导体器件结构的方法，包括以下步骤：在多晶硅栅叠层中独立地形成源极/漏极表面金属硅化物层和完全硅化金属栅极。 具体地说，在形成源极/漏极表面金属硅化物层之后并且在形成硅化金属栅极之前，在多晶硅栅极堆叠的侧壁上提供一组或多组间隔结构，以防止在其中形成附加的金属硅化物结构 源极/漏极区域在栅极盐化过程中。 所得到的半导体器件结构包括完全硅化物金属栅极，该栅极或者包含与源/漏表面金属硅化物层中的不同的金属硅化物材料，或者具有比源极/漏极表面金属硅化物层的厚度更大的厚度。 除了表面金属硅化物层之外，半导体器件结构的源极/漏极区域没有其它金属硅化物结构。

    Formation of fully silicided (FUSI) gate using a dual silicide process
    7.
    发明授权
    Formation of fully silicided (FUSI) gate using a dual silicide process 失效
    使用双重硅化物工艺形成完全硅化（FUSI）栅极

    公开(公告)号：US07273777B2

    公开(公告)日：2007-09-25

    申请号：US11195994

    申请日：2005-08-02

    申请人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

    发明人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

    IPC分类号： H01L21/8238 ,  H01L21/4763

    CPC分类号： H01L29/6656 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/51 ,  H01L29/66545

    摘要： A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.

    摘要翻译： 一种形成半导体器件结构的方法，包括以下步骤：在多晶硅栅叠层中独立地形成源极/漏极表面金属硅化物层和完全硅化金属栅极。 具体地说，在形成源极/漏极表面金属硅化物层之后并且在形成硅化金属栅极之前，在多晶硅栅极堆叠的侧壁上提供一组或多组间隔结构，以防止在其中形成附加的金属硅化物结构 源极/漏极区域在栅极盐化过程中。 所得到的半导体器件结构包括完全硅化物金属栅极，该栅极或者包含与源/漏表面金属硅化物层中的不同的金属硅化物材料，或者具有比源极/漏极表面金属硅化物层的厚度更大的厚度。 除了表面金属硅化物层之外，半导体器件结构的源极/漏极区域没有其它金属硅化物结构。

    Topography monitor
    9.
    发明授权
    Topography monitor 失效
    地形监视器

    公开(公告)号：US5952674A

    公开(公告)日：1999-09-14

    申请号：US44047

    申请日：1998-03-18

    申请人： Daniel C. Edelstein ,  Glenn A. Biery

    发明人： Daniel C. Edelstein ,  Glenn A. Biery

    IPC分类号： G01R31/316 ,  H01L23/544 ,  H01L23/58 ,  G01R31/02

    CPC分类号： H01L22/34 ,  G01R31/316 ,  H01L2924/0002

    摘要： An integrated circuit wafer topography monitor is disclosed for sensing mis-processing in the fabrication of integrated circuits. In particular, the monitor senses unacceptable variations in layer planarity resulting from over polishing, over etching, scratches and mishandling. The topography monitor may be placed within the chip active area, the chip kerf area or in unutilized areas of the wafer such as a partial chip site. The monitor is formed when, first a conformal insulator is deposited over the topography of interest. Then, runs of wire are formed in the conformal insulator by a damascene or similar process. The wire runs are formed directly above the topography of interest. A puddle of metal is formed corresponding to any unacceptably non-planar topography. The puddle electrically couples the wires together. This effects a change in the metal runs which may be sensed as an electrical short or change in resistance. The topography of interest is manipulated by design to be representative of corresponding pattern factors found in the active chip area. This then allows the electrically sensed puddles to be indicative of mis-processing to be found in the active chip area.

    摘要翻译： 公开了用于在集成电路的制造中检测误处理的集成电路晶片形貌监视器。 特别地，监视器感测到由​​于过度抛光，过蚀刻，划痕和误操作导致的层平面度的不可接受的变化。 地形监视器可以放置在芯片有效区域，芯片切口区域或晶片的未利用区域中，例如部分芯片位置。 当首先将保形绝缘体沉积在感兴趣的地形上时，形成监视器。 然后，通过镶嵌或类似的工艺在保形绝缘体中形成导线的延伸。 电线运行形成在感兴趣的地形的正上方。 形成对应于任何不可接受的非平面形貌的金属水坑。 水坑将电线电耦合在一起。 这会影响金属运行的变化，这可能会被检测为电短路或电阻变化。 感兴趣的地形由设计操纵以代表在有源芯片区域中发现的相应模式因子。 这样就允许电感的水坑指示在有源芯片区域中发现的错误处理。