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    Fully silicided metal gate semiconductor device structure
    3.
    发明授权
    Fully silicided metal gate semiconductor device structure 有权
    全硅化金属栅半导体器件结构

    公开(公告)号：US07473975B2

    公开(公告)日：2009-01-06

    申请号：US11840774

    申请日：2007-08-17

    申请人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

    发明人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

    IPC分类号： H01L29/76

    CPC分类号： H01L29/6656 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/51 ,  H01L29/66545

    摘要： A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.

    摘要翻译： 一种形成半导体器件结构的方法，包括以下步骤：在多晶硅栅叠层中独立地形成源极/漏极表面金属硅化物层和完全硅化金属栅极。 具体地说，在形成源极/漏极表面金属硅化物层之后并且在形成硅化金属栅极之前，在多晶硅栅极堆叠的侧壁上提供一组或多组间隔结构，以防止在其中形成附加的金属硅化物结构 源极/漏极区域在栅极盐化过程中。 所得到的半导体器件结构包括完全硅化物金属栅极，该栅极或者包含与源/漏表面金属硅化物层中的不同的金属硅化物材料，或者具有比源极/漏极表面金属硅化物层的厚度更大的厚度。 除了表面金属硅化物层之外，半导体器件结构的源极/漏极区域没有其它金属硅化物结构。

    Formation of fully silicided (FUSI) gate using a dual silicide process
    5.
    发明授权
    Formation of fully silicided (FUSI) gate using a dual silicide process 失效
    使用双重硅化物工艺形成完全硅化（FUSI）栅极

    公开(公告)号：US07273777B2

    公开(公告)日：2007-09-25

    申请号：US11195994

    申请日：2005-08-02

    申请人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

    发明人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

    IPC分类号： H01L21/8238 ,  H01L21/4763

    CPC分类号： H01L29/6656 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/51 ,  H01L29/66545

    摘要： A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.

    摘要翻译： 一种形成半导体器件结构的方法，包括以下步骤：在多晶硅栅叠层中独立地形成源极/漏极表面金属硅化物层和完全硅化金属栅极。 具体地说，在形成源极/漏极表面金属硅化物层之后并且在形成硅化金属栅极之前，在多晶硅栅极堆叠的侧壁上提供一组或多组间隔结构，以防止在其中形成附加的金属硅化物结构 源极/漏极区域在栅极盐化过程中。 所得到的半导体器件结构包括完全硅化物金属栅极，该栅极或者包含与源/漏表面金属硅化物层中的不同的金属硅化物材料，或者具有比源极/漏极表面金属硅化物层的厚度更大的厚度。 除了表面金属硅化物层之外，半导体器件结构的源极/漏极区域没有其它金属硅化物结构。

    Dual channel d.c. low noise measurement system and test methodology
    9.
    发明授权
    Dual channel d.c. low noise measurement system and test methodology 失效
    双通道直流 低噪声测量系统和测试方法

    公开(公告)号：US5563517A

    公开(公告)日：1996-10-08

    申请号：US442556

    申请日：1995-05-16

    申请人： Glenn A. Biery ,  Daniel M. Boyne ,  Kenneth P. Rodbell ,  Richard G. Smith ,  Michael H. Wood

    发明人： Glenn A. Biery ,  Daniel M. Boyne ,  Kenneth P. Rodbell ,  Richard G. Smith ,  Michael H. Wood

    IPC分类号： G01R31/26 ,  G01R29/26 ,  H01L21/66

    CPC分类号： G01R29/26

    摘要： A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D.U.T.). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.

    摘要翻译： 具有改进的物理布局和电气设计的测试系统允许以接近Johnson或热噪声的水平测量金属互连的1 / f噪声。 测试系统操作示例的详细描述提供了测试系统在将系统噪声降至明显低于约翰逊噪声水平的有效性的证据。 这允许由于各种应用的连接的横截面积的变化以及用于定性预测具有不同微结构的金属膜，特别是铝的电迁移寿命的噪声贡献的定量测量。 该测试系统包括一个外壳，该外壳包括若干嵌套的外壳组，其中包括在被测箱的设备内的样品烘箱，该烘箱也被包含在系统外壳内。 由直流电源供电的绕线电阻器用于提供加热，而不会干扰被测器件（D.U.T.）的1 / f噪声的测量。 偏置电路和电池组还在系统外壳内设置有单独的外壳。