公开(公告)号：US10685972B2

公开(公告)日：2020-06-16

申请号：US15514239

申请日：2014-09-26

申请人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

发明人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

IPC分类号： H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L27/115 ,  H01L49/02 ,  H01L21/02 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10

摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

公开(公告)号：US20150372005A1

公开(公告)日：2015-12-24

申请号：US14708477

申请日：2015-05-11

申请人： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul Yoo

发明人： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul Yoo

IPC分类号： H01L27/115 ,  H01L45/00 ,  H01L23/528 ,  H01L27/24

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

摘要翻译： 一种三维半导体存储器件，包括在基板上的外围电路结构，外围电路结构上的水平有源层，设置在水平有源层上的堆叠，包括多个电极，垂直穿过堆叠的垂直结构， 源区域，以及水平有源层中的拾取区域。 水平有源层包括顺序堆叠在外围电路结构上的第一，第二和第三有源半导体层。 掺杂第一和第三有源半导体层分别具有高和低杂质浓度，第二有源半导体层包括杂质扩散抑制材料。

公开(公告)号：US09515086B2

公开(公告)日：2016-12-06

申请号：US14834454

申请日：2015-08-25

申请人： Gukhyon Yon ,  Jaeyoung Ahn ,  Bio Kim ,  Young-Jin Noh ,  Kwangmin Park ,  Dongchul Yoo

发明人： Gukhyon Yon ,  Jaeyoung Ahn ,  Bio Kim ,  Young-Jin Noh ,  Kwangmin Park ,  Dongchul Yoo

IPC分类号： H01L27/115 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7926

摘要： Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.

摘要翻译： 提供三维半导体存储器件及其制造方法。 在三维半导体存储器件中，可以在衬底上形成一叠栅极电极和绝缘层，沟道结构可以延伸通过堆叠并连接至衬底。 可以在每个栅电极和沟道结构之间形成阻挡绝缘层，电荷存储层和隧道绝缘层。 隧道绝缘层可以包括具有低电荷陷阱位点密度的高k电介质层。 隧道绝缘层还可以包括第一和第二隧道绝缘层，并且高k电介质层设置在第一和第二隧道绝缘层之间。

公开(公告)号：US20160118398A1

公开(公告)日：2016-04-28

申请号：US14834454

申请日：2015-08-25

申请人： Gukhyon YON ,  Jaeyoung AHN ,  Bio KIM ,  Young-Jin NOH ,  Kwangmin PARK ,  Dongchul YOO

发明人： Gukhyon YON ,  Jaeyoung AHN ,  Bio KIM ,  Young-Jin NOH ,  Kwangmin PARK ,  Dongchul YOO

IPC分类号： H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L27/11582 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7926

摘要： Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.

摘要翻译： 提供三维半导体存储器件及其制造方法。 在三维半导体存储器件中，可以在衬底上形成一叠栅极电极和绝缘层，沟道结构可以延伸通过堆叠并连接至衬底。 可以在每个栅电极和沟道结构之间形成阻挡绝缘层，电荷存储层和隧道绝缘层。 隧道绝缘层可以包括具有低电荷陷阱位点密度的高k电介质层。 隧道绝缘层还可以包括第一和第二隧道绝缘层，并且高k电介质层设置在第一和第二隧道绝缘层之间。

公开(公告)号：US09997530B2

公开(公告)日：2018-06-12

申请号：US14708477

申请日：2015-05-11

申请人： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul Yoo

发明人： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul Yoo

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/24 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11575 ,  H01L45/00

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

公开(公告)号：US20170287929A1

公开(公告)日：2017-10-05

申请号：US15514239

申请日：2014-09-26

申请人： Sunggil KIM ,  Phil Ouk NAM ,  Gukhyon YON ,  Sunghae LEE ,  Woojin JANG ,  Dongchul YOO ,  Hunhyeong LIM ,  Junggeun JEE ,  Kihyun HWANG

发明人： Sunggil KIM ,  Phil Ouk NAM ,  Gukhyon YON ,  Sunghae LEE ,  Woojin JANG ,  Dongchul YOO ,  Hunhyeong LIM ,  Junggeun JEE ,  Kihyun HWANG

IPC分类号： H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10

CPC分类号： H01L27/11582 ,  H01L21/0206 ,  H01L21/31116 ,  H01L27/115 ,  H01L27/1157 ,  H01L28/00 ,  H01L29/1037 ,  H01L29/40117

摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.