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    Methods and apparatus for performing slew dependent signal bounding for signal timing analysis
    1.
    发明授权
    Methods and apparatus for performing slew dependent signal bounding for signal timing analysis 失效
    用于执行信号时序分析的与电压相关的信号限幅的方法和装置

    公开(公告)号：US06430731B1

    公开(公告)日：2002-08-06

    申请号：US09368479

    申请日：1999-08-04

    Applicant: Jin-Fuw Lee ,  Daniel Lawrence Ostapko ,  Jeffrey Paul Soreff ,  Chak-Kuen Wong

    Inventor： Jin-Fuw Lee ,  Daniel Lawrence Ostapko ,  Jeffrey Paul Soreff ,  Chak-Kuen Wong

    IPC: G06F1750

    CPC classification number: G06F17/5031

    Abstract: Methods and apparatus for use in signal timing analysis with respect to a circuit having at least one gate are provided. In one aspect, the invention includes the step of determining a first constraint slew sensitivity value and a second constraint slew sensitivity value for the at least one gate according to a specified bounding technique. Then, a representative signal for the gate is computed in accordance with the first and second values including an arrival time and slew rate, wherein the representative signal bounds signal paths by bounding a maximum slew sensitivity path and a minimum slew sensitivity path. Such a representative signal may be computed for a worst case late-mode analysis and/or a best case early-mode analysis. The bounding technique may be selected by a user at the time the user inputs the schematic of the circuit on which timing analysis is to be performed. The invention provides for the use of bounding techniques such as, for example, maximum slew, minimum slew, half envelope, full envelope, modified half envelope, modified max slew, modified min slew, least upper bound, and greatest lower bound. The invention may preferably be employed in accordance with static timing analysis associated with VLSI circuit design.

    Abstract translation: 提供了关于具有至少一个栅极的电路的信号时序分析中使用的方法和装置。 一方面，本发明包括根据指定的边界技术确定至少一个门的第一约束转换灵敏度值和第二约束转换灵敏度值的步骤。 然后，根据包括到达时间和转换速率的第一和第二值来计算门的代表信号，其中代表信号通过限制最大转换灵敏度路径和最小转换灵敏度路径来限制信号路径。 可以针对最坏情况的后期模式分析和/或最佳情况的早期模式分析来计算这样的代表性信号。 边界技术可以由用户在用户输入将执行定时分析的电路的原理图时选择。 本发明提供了使用边界技术，例如最大旋转，最小旋转，半包络，全包络，修改的半包络，修改的最大旋转，修改的最小压摆，最小上限和最大下限。 本发明可以优选地根据与VLSI电路设计相关的静态时序分析来使用。

    METHOD OF INTEGRATED CIRCUIT CHIP FABRICATION AND PROGRAM PRODUCT THEREFOR
    2.
    发明申请
    METHOD OF INTEGRATED CIRCUIT CHIP FABRICATION AND PROGRAM PRODUCT THEREFOR 有权
    集成电路芯片制造方法及其程序产品

    公开(公告)号：US20100318956A1

    公开(公告)日：2010-12-16

    申请号：US12482504

    申请日：2009-06-11

    Applicant: Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien ,  Rama N. Singh

    Inventor： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien ,  Rama N. Singh

    IPC: G06F17/50

    CPC classification number: G03F1/36

    Abstract: A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.

    Abstract translation: 一种用于集成电路（IC）芯片制造，物理设计系统及其程序产品的物理设计方法。 设计形状被分段为光学邻近校正（OPC）的段，并确定段的谐波平均值。 根据形状确定电气意图，并为段确定谐波平均值。 可以基于使用谐波平均成本函数测量的移动段的对谐波平均值的影响来移动段。 最后分段形状传递给OPC。

    SYSTEM AND METHOD FOR EMPLOYING PATTERNING PROCESS STATISTICS FOR GROUND RULES WAIVERS AND OPTIMIZATION
    3.
    发明申请
    SYSTEM AND METHOD FOR EMPLOYING PATTERNING PROCESS STATISTICS FOR GROUND RULES WAIVERS AND OPTIMIZATION 有权
    用于接地规则的绘图过程统计的系统和方法和优化

    公开(公告)号：US20080301624A1

    公开(公告)日：2008-12-04

    申请号：US12175097

    申请日：2008-07-17

    Applicant: Fook-Luen Heng ,  Mark Alan Lavin ,  Jin-Fuw Lee ,  Chieh-yu Lin ,  Jawahar Pundalik Nayak ,  Rama Nand Singh

    Inventor： Fook-Luen Heng ,  Mark Alan Lavin ,  Jin-Fuw Lee ,  Chieh-yu Lin ,  Jawahar Pundalik Nayak ,  Rama Nand Singh

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.

    Abstract translation: 使用图案化处理统计来评估交叉区域分析的布局的系统和方法包括对布局应用光学近似校正（OPC），模拟由掩模形成的图像并应用图案化过程变化分布来影响和确定纠正措施以改进和 优化布局符合规则。 通过基于交叉区域的多个处理创建直方图，将过程变化分布映射到交叉区域分布。 使用直方图分析交叉区域，以提供基本规则豁免和优化。

    Clock distribution network with dual wire routing
    5.
    发明授权
    Clock distribution network with dual wire routing 失效
    时钟分配网络，双线路

    公开(公告)号：US6144224A

    公开(公告)日：2000-11-07

    申请号：US348041

    申请日：1999-07-06

    Applicant: Jin-Fuw Lee ,  Daniel Lawrence Ostapko

    Inventor： Jin-Fuw Lee ,  Daniel Lawrence Ostapko

    IPC: G06F1/10 ,  H03K3/86 ,  H03K19/00

    CPC classification number: G06F1/10 ,  H03K3/86

    Abstract: A new clock distribution network design for VLSI circuits which effectively reduces skew without the area and power penalty associated with prior clock designs. Two wires emanating from the clock in opposite directions or, alternatively, two wires connected in series and running parallel, are used to route clock signals from the clock source to the next routing segment. The next routing segment routes clock signals to the tapping point near the circuit component by two emanated wires from the previous routing segment. Clock signals from the routing segments are fed through two-input NOR gates (alternatively, two-input NAND gates) to the clock pins. The clock signal arrival time is roughly equal to the simultaneous switching gate delay plus the average arrival times from the two paths, which turns out approximately the same across different tapping points, thus minimizing clock skews. Narrow wires may be used for routing, resulting in moderate power consumption.

    Abstract translation: 一种用于VLSI电路的新型时钟分配网络设计，可有效减少偏移，而无需与现有时钟设计相关的面积和功耗。 使用从时钟相反方向发出的两根线，或者两根并联连接并联并联的两条线，将时钟信号从时钟源路由到下一个路由段。 下一个路由段将时钟信号通过来自先前路由段的两条发射线路将时钟信号路由到电路组件附近的分接点。 来自路由段的时钟信号通过双输入NOR门（或者两个输入NAND门）馈送到时钟引脚。 时钟信号到达时间大致等于同时切换门延迟加上两条路径的平均到达时间，这两条路径的平均到达时间在不同的分接点之间大致相同，从而最小化时钟偏移。 窄导线可用于布线，导致中等功耗。

    Optimizing integrated circuit chip designs for optical proximity correction
    7.
    发明授权
    Optimizing integrated circuit chip designs for optical proximity correction 有权
    优化用于光学邻近校正的集成电路芯片设计

    公开(公告)号：US08122387B2

    公开(公告)日：2012-02-21

    申请号：US12482504

    申请日：2009-06-11

    Applicant: Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien, legal representative ,  Rama N. Singh

    Inventor： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Rama N. Singh

    IPC: G06F17/50

    CPC classification number: G03F1/36

    Abstract: A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.

    Abstract translation: 一种用于集成电路（IC）芯片制造，物理设计系统及其程序产品的物理设计方法。 设计形状被分段为光学邻近校正（OPC）的段，并确定段的谐波平均值。 根据形状确定电气意图，并为段确定谐波平均值。 可以基于使用谐波平均成本函数测量的移动段的对谐波平均值的影响来移动段。 最后分段形状传递给OPC。

    CA resistance variability prediction methodology
    9.
    发明授权
    CA resistance variability prediction methodology 有权
    CA抗性变异性预测方法

    公开(公告)号：US07831941B2

    公开(公告)日：2010-11-09

    申请号：US11968458

    申请日：2008-01-02

    Applicant: Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    Inventor： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.

    Abstract translation: 一种用于获得电子电路中CA电阻改进预测的方法，特别是改进的CA电阻模型，适用于捕获大于预期的“超出规范”状态。 在一个实施例中，实现了一种新颖的分层方案，其编码为电路设计者提供了相当好的设计选项，用于处理大的CA变异性，如通过设计手册所看到的。 开发用于建模CA可变电阻现象影响的工具为开发人员提供了一种电阻模型，如常规已知的，使用新的CA模型Basis进行修改，包括新颖的CA内在电阻模型，以及新颖的CA布局分层模型。

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