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公开(公告)号：US20130003475A1
公开(公告)日：2013-01-03
申请号：US13171811
申请日：2011-06-29
IPC分类号： G11C8/18
CPC分类号： G06F3/0605 , G06F3/0659 , G06F3/0673 , G06F12/00 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/40 , G11C11/40622 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , G11C2207/2272
摘要： Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.
摘要翻译： 包括：由存储器控制器对DDR存储器模块的预定地址执行一个或多个写入操作，包括向DDR存储器模块发送预定量的数据的数据 预定模式以及数据选通信号; 由所述存储器控制器执行来自所述DDR存储器模块的预定地址的多个读取操作，包括捕获从所述DDR存储器模块发送的数据; 以及由存储器控制器根据读取操作所捕获的数据确定读取调整值和写入调整值。
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公开(公告)号：US07944931B2
公开(公告)日：2011-05-17
申请号：US11776162
申请日：2007-07-11
CPC分类号： H04L49/9042 , H04L49/90 , H04L2012/5681
摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.
摘要翻译： 存储器子系统包括数据存储0和数据存储1.每个数据存储分区为N个缓冲区，N> 1。 存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。 两个缓冲器对格式用于形成存储器增量。 第一格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二个格式从Data Store 1中选择第一个缓冲区，并从Data Store 0中选择一个第二个缓冲区。控制器选择一个用于存储数据的缓冲区 基于诸如交换单元之类的递送机制中的数据的配置。
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公开(公告)号：US07937533B2
公开(公告)日：2011-05-03
申请号：US12114792
申请日：2008-05-04
CPC分类号： G06F12/0815 , G06F2212/507
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 该设计结构通常包括计算机系统，其包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供与可读取总数的所选百分比相对应的推测读取阈值的电路 推测性发布，以及根据推测读取阈值混合需求读取和推测读取的电路。
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4.发明授权Data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode 失效在可变延迟模式下工作的FBDIMM存储系统中的数据总线带宽调度公开(公告)号：US07660952B2
公开(公告)日：2010-02-09
申请号：US11680695
申请日：2007-03-01
IPC分类号： G06F12/06
CPC分类号： G06F13/4243
摘要： A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.
摘要翻译： 一种用于在FBDIMM存储器子系统中使用可变等待时间模式来调度数据请求的服务的方法和系统。 调度算法预先计算连接到所有DRAM缓冲器芯片的数据的返回时间数据，并将返回时间数据存储在表中。 返回时间数据表示为在每个向量中一位等于“1”的一组数据返回时间二进制向量。 对于每个接收到的数据请求，存储器控制器检索适当的返回时间向量。 此外，调度算法利用表示所有执行请求的数据返回时间向量的汇编的更新历史向量，以确定接收到的请求是否对执行请求产生冲突。 通过计算和利用每个请求的分数，调度算法重新排序和调度所选择的请求的执行，以尽可能地保留尽可能多的数据总线带宽，同时避免冲突。
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5.发明授权Method and apparatus for reducing latency associated with read operations in a memory system 失效用于减少与存储器系统中的读取操作相关联的延迟的方法和装置公开(公告)号：US07657771B2
公开(公告)日：2010-02-02
申请号：US11621201
申请日：2007-01-09
CPC分类号： G06F13/1689
摘要： Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in accordance with a pre-determined delay such that the early read indicator is passed to a bus in advance of the read data; and dynamically adjusting the pre-determined delay using an adjustment delay circuit, the pre-determined delay being adjusted responsive to a change in operational speed of the bus or change in operational speed of a processor coupled to the bus.
摘要翻译： 提供了用于减少与处理器存储器系统中的读取操作相关联的延迟的方法和系统。 在一个实现中，该方法包括从存储器接收对应于读取数据的早期指示符，根据预定延迟延迟早期指示符，使得早期读取指示符在读取数据之前被传递到总线; 以及使用调整延迟电路动态调整预定延迟，响应于总线的操作速度的变化或耦合到总线的处理器的操作速度的改变来调整预定的延迟。
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公开(公告)号：US20100005214A1
公开(公告)日：2010-01-07
申请号：US12165814
申请日：2008-07-01
CPC分类号： G06F13/405 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for enhancing bus efficiency and utilization in a memory system. The communication interface device includes a first bus interface to communicate on a high-speed bus, a second bus interface to communicate on a lower-speed bus, and clock ratio logic configurable to support multiple clock ratios between the high-speed bus and the lower-speed bus. The clock ratio logic reduces a high-speed clock frequency received at the first bus interface and outputs a reduced ratio of the high-speed clock frequency on the lower-speed bus via the second bus interface supporting variable frame sizes.
摘要翻译： 一种用于提高存储系统中总线效率和利用率的通信接口设备，系统，方法和设计结构。 通信接口设备包括用于在高速总线上通信的第一总线接口，用于在低速总线上进行通信的第二总线接口以及可配置为支持高速总线与低速总线之间的多个时钟比的时钟比率逻辑 高速公交车 时钟比率逻辑降低了在第一总线接口处接收的高速时钟频率，并且经由支持可变帧大小的第二总线接口输出低速总线上的高速时钟频率的减小的比率。
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7.发明申请METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC SELECTIVE MEMORY MIRRORING 有权用于动态选择记忆镜的方法，系统和计算机程序产品公开(公告)号：US20090216985A1
公开(公告)日：2009-08-27
申请号：US12035695
申请日：2008-02-22
申请人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
发明人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
IPC分类号： G06F12/02
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/20 , G06F12/0246 , G06F2211/1088
摘要： Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.
摘要翻译： 为固态设备中的动态选择性存储器镜像提供了方法，系统和计算机程序产品。 保留一定量的内存。 用于在保留的存储器中选择镜像的存储器的部分是动态确定的。 存储器的选定部分包含关键区域。 存储器的选定部分被镜像在保留的存储器中。
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公开(公告)号：US20090150618A1
公开(公告)日：2009-06-11
申请号：US12115146
申请日：2008-05-05
IPC分类号： G06F12/02
CPC分类号： G06F12/0862
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 该设计结构通常包括计算机系统，其包括CPU，存储设备，用于提供与可推测发布的对存储设备的访问总数的所选百分比相对应的推测访问阈值的电路，以及用于混合需求的电路 根据投机访问阈值访问和推测访问。
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9.发明申请MEMORY SYSTEM WITH APPARATUS AND METHOD TO ENABLE BALANCED BANDWIDTH UTILIZATION 失效具有装置的存储系统和使用平衡带宽利用的方法公开(公告)号：US20080240110A1
公开(公告)日：2008-10-02
申请号：US11776162
申请日：2007-07-11
IPC分类号： H04L12/56
CPC分类号： H04L49/9042 , H04L49/90 , H04L2012/5681
摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.
摘要翻译： 内存子系统包括数据存储0和数据存储1。 每个数据存储区分为N个缓冲区，N> 1。 存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。 两个缓冲器对格式用于形成存储器增量。 第一种格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二种格式从Data Store 1中选择第一个缓冲区，从Data Store 0中选择第二个缓冲区。 控制器基于诸如交换单元之类的传送机制中的数据的配置来选择用于存储数据的缓冲器对。
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10.发明申请STRUCTURE FOR REDUCING LATENCY ASSOCIATED WITH READ OPERATIONS IN A MEMORY SYSTEM 失效用于减少与存储器系统中的读操作相关的延迟的结构公开(公告)号：US20080209095A1
公开(公告)日：2008-08-28
申请号：US12114787
申请日：2008-05-04
IPC分类号： G06F13/36
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.
摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 设计结构通常包括处理器存储器系统，其可以包括处理器和通过总线与处理器通信的存储器控制器。 存储器控制器可以包括延迟电路，用于接收对应于来自存储器的读取数据的早期读取指示符，延迟电路根据预定的延迟来延迟早期读取指示符，使得早期读取指示符被传递到总线 以及延迟调整电路，用于响应于处理器或总线的操作速度的变化来动态地调整与延迟电路相关联的预定延迟。
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