-
公开(公告)号：US12232435B2
公开(公告)日：2025-02-18
申请号：US18130184
申请日：2023-04-03
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
-
公开(公告)号：US20250040165A1
公开(公告)日：2025-01-30
申请号：US18911058
申请日：2024-10-09
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Arnaud REGNIER , Dann MORILLON , Franck JULIEN , Marjorie HESSE
IPC: H01L29/66 , H01L21/28 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/786
Abstract: A MOS transistor including a substrate, a conductive having lateral walls, drain and source regions, and spacers having an upper surface such that the spacers are buried in the substrate and are position between the conductive gate and the drain and source regions is provided. The spacers are each cuboid-shaped and have a width that is constant along the spacers height and independent from a height of the conductive gate. A device including the MOS transistor and a method of manufacture for producing a right-hand portion and a left-hand portion of a MOS transistor is also provided.
-
公开(公告)号：US12197557B2
公开(公告)日：2025-01-14
申请号：US17454231
申请日：2021-11-09
Inventor： Antonino Mondello , Stefano Catalano , Cyril Pascal
Abstract: According to one aspect, a system-on-a-chip is proposed which includes a memory storage, a computation circuit, a comparison circuit, and a validation circuit. The memory storage is configured to store an external software module. The computation circuit is configured to compute several modified software modules from the external software module and compute check values by iteration until obtaining a final check value. Each check value is computed at least from a given modified software module and a check value previously computed, starting with a predefined initial check value. The comparison circuit is configured to compare the final check value to an expected value stored in the system-on-a-chip. The validation circuit is configured to validate the external software module when the final check value is equal to the expected value.
-
公开(公告)号：US20250015188A1
公开(公告)日：2025-01-09
申请号：US18887645
申请日：2024-09-17
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak MARZAKI , Romeric GAY
IPC: H01L29/78 , H01L21/28 , H01L27/088 , H01L29/423 , H01L29/66 , H01L29/788 , H10B41/35
Abstract: A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.
-
公开(公告)号：US12143108B2
公开(公告)日：2024-11-12
申请号：US17812127
申请日：2022-07-12
Inventor： Francesco La Rosa , Marco Bildgen
IPC: H03K19/17768 , H03K19/08 , H03K19/1776 , H04L9/32
Abstract: In an embodiment an integrated device includes a first physical unclonable function module configured to generate an initial data group and management module configured to generate an output data group from at least the initial data group, authorize only D successive deliveries of the output data group on a first output interface of the device, D being a non-zero positive integer, and prevent any new generation of the output data group.
-
Patent Agency Ranking
公开(公告)号：US12125533B2
公开(公告)日：2024-10-22
申请号：US17812122
申请日：2022-07-12
Inventor： Francesco La Rosa , Marco Bildgen
CPC classification number: G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/26 , H10B41/35
Abstract: In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.
-
公开(公告)号：US12124713B2
公开(公告)日：2024-10-22
申请号：US18057390
申请日：2022-11-21
Inventor： Francesco Bombaci , Andrea Tosoni
IPC: G06F3/06
CPC classification number: G06F3/0629 , G06F3/0622 , G06F3/0665 , G06F3/0679
Abstract: A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.
-
公开(公告)号：US20240296253A1
公开(公告)日：2024-09-05
申请号：US18661060
申请日：2024-05-10
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco La Rosa
IPC: G06F21/75 , G06F21/72 , G11C11/4096 , H01L27/088 , H03K19/17768
CPC classification number: G06F21/75 , G06F21/72 , G11C11/4096 , H01L27/0883 , H03K19/17768
Abstract: An embodiment system comprises a physical unclonable function device, wherein the device comprises a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution, and a processing circuit configured to deliver, to an output interface of the device, a group of output data based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly.
-
公开(公告)号：US12081224B2
公开(公告)日：2024-09-03
申请号：US17807452
申请日：2022-06-17
Inventor： Laurent Meunier , Vincent Pascal Onde
CPC classification number: H03L7/24 , G06F1/14 , G06F9/4812 , H03L7/0992
Abstract: In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.
-
公开(公告)号：US20240276894A1
公开(公告)日：2024-08-15
申请号：US18646334
申请日：2024-04-25
Inventor： Philippe BOIVIN , Roberto SIMOLA , Yohann MOUSTAPHA-RABAULT
CPC classification number: H10N70/231 , H10B63/80 , H10N70/021 , H10N70/063 , H10N70/066 , H10N70/068 , H10N70/882 , H10N70/883
Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
-
-
-
-
-
-
-
-
-
Search Results
1622
records
(took 0.019 seconds)
