公开(公告)号：US20250169169A1

公开(公告)日：2025-05-22

申请号：US19023152

申请日：2025-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H10D84/83 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H10D30/01 ,  H10D62/10 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03 ,  H10D86/01 ,  H10D89/10

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

公开(公告)号：US20250169140A1

公开(公告)日：2025-05-22

申请号：US19023210

申请日：2025-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Fu-Jung Chuang ,  Ya-Yin Hsiao ,  Nan-Yuan Huang

IPC: H10D64/01 ,  H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/324 ,  H10D30/01 ,  H10D30/60 ,  H10D62/13 ,  H10D64/27 ,  H10D64/66 ,  H10D64/68

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

公开(公告)号：US20250169119A1

公开(公告)日：2025-05-22

申请号：US19026289

申请日：2025-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H10D30/69 ,  H01L21/02 ,  H10D62/10 ,  H10D64/01

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

公开(公告)号：US20250159916A1

公开(公告)日：2025-05-15

申请号：US19019409

申请日：2025-01-13

Applicant: UNITED MICROELECTRONICS CORP,

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H10D30/01 ,  H01L21/324 ,  H01L21/768 ,  H10D30/47 ,  H10D62/85

Abstract: A high electron mobility transistor includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, a gate structure disposed on the barrier layer, a source contact structure and a drain contact structure disposed on the barrier layer at two sides of the gate structure, and extending through the barrier layer to directly contact the channel layer, and a gate contact structure disposed on the gate structure. The source contact structure, the drain contact structure, and the gate contact structure respectively include a liner and a metal layer directly disposed on the liner. The metal layer comprises a metal material doped with a first additive, and a weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US20250151366A1

公开(公告)日：2025-05-08

申请号：US18531679

申请日：2023-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zi-Ting Huang ,  Ching-Ling Lin ,  Wen-An Liang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a core region and an input/output (I/O) region and then forming a first metal gate on the core region and a second metal gate on the I/O region. Preferably, the first metal gate includes a first gate dielectric layer, the second metal gate includes a second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer having different shapes such that the first gate dielectric layer includes an I-shape and the second gate dielectric layer includes a U-shape.

公开(公告)号：US12293941B2

公开(公告)日：2025-05-06

申请号：US17835983

申请日：2022-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H10D64/00 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

Abstract: A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.

公开(公告)号：US20250142895A1

公开(公告)日：2025-05-01

申请号：US18523894

申请日：2023-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Lun Jheng ,  Po-Jui Chiang ,  Chao-Sheng Cheng ,  Ming-Jen Chang ,  Ko-Chin Chang ,  Yu-Ming Liu

IPC: H01L29/423 ,  H01L29/66 ,  H10B41/30

Abstract: An embedded flash memory structure, including a semiconductor substrate, an erase gate on the semiconductor substrate, two floating gates respectively at two sides of the erase gate on the semiconductor substrate, two word lines respectively at outer sides of the two floating gates, and two metal control gates respectively on the two floating gates, wherein a sacrificial layer is at at least one side of the metal control gate, and the sacrificial layer is between the metal control gate and the erase gate or between the metal control gate and the word line.

公开(公告)号：US20250142849A1

公开(公告)日：2025-05-01

申请号：US18513657

申请日：2023-11-20

Applicant: UNITED MICROELECTRONICS cORP.

Inventor： Hsin-Hsien Chen ,  Kuo-Hsing Lee ,  Chih-Kai Kang ,  Sheng-Yuan Hsueh

IPC: H01L27/06

Abstract: The invention provides a capacitor structure with a fin structure, which comprises a fin structure located on a substrate, a lower electrode layer, a high dielectric constant layer and an upper electrode layer stacked on the fin structure in sequence, and an ion doped region located in the substrate below the fin structure, and a top surface of the ion doped region is aligned with a bottom surface of the fin structure.

公开(公告)号：US20250141701A1

公开(公告)日：2025-05-01

申请号：US18518567

申请日：2023-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin

IPC: H04L9/32 ,  H01L27/06 ,  H01L29/94

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first providing a PUF cell array having a plurality of unit cells, in which each of the unit cells includes a transistor and a first metal-oxide semiconductor capacitor (MOSCAP) and a second MOSCAP coupled to the transistor. Next, a voltage is transmitted through the transistor to the first MOSCAP and the second MOSCAP and whether the first MOSCAP or the second MOSCAP reaches a breakdown is determined.

公开(公告)号：US12290005B2

公开(公告)日：2025-04-29

申请号：US18679437

申请日：2024-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Si-Han Tsai ,  Che-Wei Chang ,  Jing-Yin Jhang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/85 ,  H10N50/01

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.