公开(公告)号：US07016257B2

公开(公告)日：2006-03-21

申请号：US10790262

申请日：2004-03-01

Applicant: Nam-Seog Kim ,  Uk-Rae Cho ,  Yong-Jin Yoon

Inventor： Nam-Seog Kim ,  Uk-Rae Cho ,  Yong-Jin Yoon

IPC: G11C8/00

CPC classification number: G11C29/12015 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C29/14

Abstract: A semiconductor memory device comprising: an array of memory cells; an address input circuit for receiving an external address in response to an address clock signal; a selecting circuit for selecting a memory cell in response to an address output from the address input circuit; a data output circuit for outputting the data read out from the selected memory cell in response to first and second data clock signals; and an internal clock generating circuit for generating the address clock signal and the first and second data clock signals in response to an external clock signal and a complementary clock signal thereof, wherein the address clock signal and the first and second data clock signals have twice the frequency (or half the period) of the external clock signal when in a test mode.

Abstract translation: 一种半导体存储器件，包括：存储器单元阵列; 地址输入电路，用于响应于地址时钟信号接收外部地址; 选择电路，用于响应于从地址输入电路输出的地址来选择存储单元; 数据输出电路，用于响应于第一和第二数据时钟信号输出从所选存储单元读出的数据; 以及内部时钟发生电路，用于响应于外部时钟信号及其互补时钟信号产生地址时钟信号和第一和第二数据时钟信号，其中地址时钟信号和第一和第二数据时钟信号具有两倍 在测试模式时外部时钟信号的频率（或一半周期）。

公开(公告)号：US6114885A

公开(公告)日：2000-09-05

申请号：US138641

申请日：1998-08-24

Applicant: Seung-Kweon Yang ,  Yong-Jin Yoon

Inventor： Seung-Kweon Yang ,  Yong-Jin Yoon

IPC: G11C11/417 ,  H03H11/28 ,  H03K19/00 ,  H03K3/00

CPC classification number: H03K19/0005

Abstract: Integrated driver circuits include a pull-up circuit having a first plurality of PMOS pull-up transistors therein which are selectively enabled by a first multi-bit impedance control signal. This first multi-bit impedance control signal is a function of a first variable resistance device. A pull-down circuit is also provided. The pull-down circuit has a first plurality of NMOS pull-down transistors therein which are selectively enabled by a second multi-bit impedance control signal. This second multi-bit impedance control signal is a function of a resistance of a second variable resistance device. The pull-up circuit and pull-down circuit have commonly connected outputs. In particular, the pull-up circuit has a first impedance which is a function of a digital value of the first multi-bit impedance control signal and the pull-down circuit has a second impedance which is a function of a digital value of the second multi-bit impedance control signal. Moreover, the first variable resistance device and the second variable resistance device may be external to the pull-up circuit and the pull-up circuit, respectively. The resistances of the first and second variable resistance devices may also be independently controllable as separate potentiometers.

Abstract translation: 集成驱动器电路包括其中具有第一多个PMOS上拉晶体管的上拉电路，其被第一多位阻抗控制信号选择性地使能。 该第一多位阻抗控制信号是第一可变电阻装置的功能。 还提供了一个下拉电路。 下拉电路具有其中的第一多个NMOS下拉晶体管，其被第二多位阻抗控制信号选择性地使能。 该第二多位阻抗控制信号是第二可变电阻装置的电阻的函数。 上拉电路和下拉电路具有共同连接的输出。 特别地，上拉电路具有第一阻抗，其是第一多位阻抗控制信号的数字值的函数，并且下拉电路具有作为第二多位阻抗控制信号的数字值的函数的第二阻抗 多位阻抗控制信号。 此外，第一可变电阻装置和第二可变电阻装置可以分别在上拉电路和上拉电路的外部。 第一和第二可变电阻器件的电阻也可独立地作为单独的电位计来控制。

公开(公告)号：US5894233A

公开(公告)日：1999-04-13

申请号：US965562

申请日：1997-11-06

Applicant: Yong-jin Yoon

Inventor： Yong-jin Yoon

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/08

CPC classification number: G11C7/062

Abstract: Sense amplifiers for integrated circuit memory devices including a bipolar transistor voltage gain input buffer and a first effect transistor latch circuit. The bipolar transistor voltage gain input buffer is responsive to a pair of complementary input signals from a memory cell, to amplify the voltage differential between the pair of complementary input signals. The field effect transistor latch circuit is responsive to the bipolar transistor voltage gain input buffer, to latch the voltage differential so amplified, and thereby produce a pair of complementary output signals.

Abstract translation: 用于集成电路存储器件的感测放大器，包括双极晶体管电压增益输入缓冲器和第一效应晶体管锁存电路。 双极晶体管电压增益输入缓冲器响应来自存储单元的一对互补输入信号，以放大该对互补输入信号之间的电压差。 场效应晶体管锁存电路响应双极晶体管电压增益输入缓冲器，锁存经过放大的电压差，从而产生一对互补输出信号。

公开(公告)号：US08643420B2

公开(公告)日：2014-02-04

申请号：US13527214

申请日：2012-06-19

Applicant: Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

Inventor： Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC classification number: H03K5/05

Abstract: An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.

Abstract translation: 集成电路装置包括：时钟延迟电路，被配置为接收时钟信号和脉冲信号并从其产生输出信号。 时钟延迟电路被配置为响应于时钟信号的第一状态而将输出信号转换到第一状态，并且响应于脉冲信号的第一状态转换而将输出信号转变到第二状态。 集成电路装置还包括脉冲发生器电路，其被配置为接收时钟信号和输出信号并从其产生脉冲信号。 脉冲发生器电路被配置为响应于时钟信号向第二状态的转变而产生脉冲信号中的第一状态转换，并且响应于输出信号向第二状态的转变而产生脉冲信号中的第二状态转换 州。

公开(公告)号：US08578227B2

公开(公告)日：2013-11-05

申请号：US12944787

申请日：2010-11-12

Applicant: Young-Jae Son ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Young-Jae Son ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: G01R31/28

CPC classification number: G01R31/31725 ,  G06F11/24

Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.

Abstract translation: 用于片上系统的测试装置包括顺序逻辑电路和测试电路。 顺序逻辑电路通过根据串行时钟信号和串行使能信号将串行输入信号转换为并行格式产生测试输入信号，并通过将测试输出信号转换成串行格式来响应于 串行时钟信号和串行使能信号。 测试电路包括至少一个延迟单元，其与执行片上系统的原始功能的逻辑电路分离，响应于系统时钟信号，使用测试输入信号对至少一个延迟单元执行延迟测试 和测试使能信号，并将测试输出信号提供给顺序逻辑电路，其中测试输出信号表示延迟测试的结果。

公开(公告)号：US07586775B2

公开(公告)日：2009-09-08

申请号：US11850130

申请日：2007-09-05

Applicant: Sang-beom Kang ,  Yong-jin Yoon ,  Qi Wang

Inventor： Sang-beom Kang ,  Yong-jin Yoon ,  Qi Wang

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/009

Abstract: A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater than the first magnitude. The first circuit block selectively receives the first voltage or the second voltage through an input node. The discharge unit discharges the input node between a time point where the input node has been charged with the second voltage and a time point where the input node receives the first voltage.

Abstract translation: 非易失性存储器件包括第一电压产生单元，第二电压产生单元，第一电路块和放电单元。 第一电压产生单元产生具有第一量值的第一电压。 第二电压产生单元产生具有大于第一幅值的第二幅度的第二电压。 第一电路块通过输入节点选择性地接收第一电压或第二电压。 放电单元在输入节点已经被充电的时间点与第二电压之间和输入节点接收到第一电压的时间点之间对输入节点进行放电。

公开(公告)号：US07154312B2

公开(公告)日：2006-12-26

申请号：US11031129

申请日：2005-01-07

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: H03L7/00

CPC classification number: H03L7/0812 ,  H03K5/133 ,  H03K5/135

Abstract: An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.

Abstract translation: 提供了一种用于产生用于获取精确同步的内部时钟信号的装置。 该装置包括：输入缓冲器，用于缓冲外部时钟信号以输出第一参考时钟信号; 延迟补偿电路，用于延迟第一参考时钟信号; 前向延迟阵列 镜控制电路，包括用于检测与第二参考时钟信号同步的延迟时钟信号的多个相位检测器; 后向延迟阵列 以及产生内部时钟信号的输出缓冲器。 可以通过最小化参考时钟信号的延迟和失真来产生与参考时钟信号精确同步的内部时钟信号。

公开(公告)号：US20050194995A1

公开(公告)日：2005-09-08

申请号：US11071433

申请日：2005-03-03

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: H03F3/45 ,  G11C7/10

CPC classification number: H03K3/356139

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

Abstract translation: 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

公开(公告)号：US06617894B2

公开(公告)日：2003-09-09

申请号：US10081359

申请日：2002-02-20

Applicant: Yong-Jin Yoon ,  Uk-Rae Cho ,  Jung-Woo Park ,  Kwang-Jin Lee ,  Nam-Seog Kim

Inventor： Yong-Jin Yoon ,  Uk-Rae Cho ,  Jung-Woo Park ,  Kwang-Jin Lee ,  Nam-Seog Kim

IPC: H03L700

CPC classification number: G06F1/10 ,  H03K5/135

Abstract: A circuit includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.

公开(公告)号：US06507224B1

公开(公告)日：2003-01-14

申请号：US10038171

申请日：2002-01-03

Applicant: Jong Cheol Lee ,  Yong Jin Yoon ,  Kwang Jin Lee

Inventor： Jong Cheol Lee ,  Yong Jin Yoon ,  Kwang Jin Lee

IPC: G11C2702

CPC classification number: H03K3/356139 ,  H03K3/012 ,  H03K3/356156

Abstract: An input receiver capable of sensing and amplifying an external signal having a very small swing input signal. The input receiver comprises a clock sampled amplifier for receiving a clock signal and a reference signal, respectively, in response to a first state of a clock signal and a delayed sampling clock signal, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock and delayed sampling clock signals to a second state; and a pulse generator for pre-charging a power source voltage and selectively pulling down the pre-charged signals to produce a pulse signal, in response to the second state of the delayed sampling clock signal and outputs of the clock sampled amplifier.

Abstract translation: 一种能够感测和放大具有非常小的摆动输入信号的外部信号的输入接收器。 输入接收机包括响应于时钟信号和延迟采样时钟信号的第一状态分别接收时钟信号和参考信号的时钟采样放大器，并且用于放大和采样外部信号与 分别响应于时钟的转变和延迟的采样时钟信号到第二状态的参考信号; 以及脉冲发生器，用于响应于延迟的采样时钟信号的第二状态和时钟采样放大器的输出，对电源电压进行预充电并选择性地拉低预充电信号以产生脉冲信号。