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    METHOD FOR CHAINING MEDIA PROCESSING
    3.
    发明申请
    METHOD FOR CHAINING MEDIA PROCESSING 有权
    用于链接媒体处理的方法

    公开(公告)号：US20170039672A1

    公开(公告)日：2017-02-09

    申请号：US14816508

    申请日：2015-08-03

    Applicant: Apple Inc.

    Inventor： Timothy J. Millet ,  Manu Gulati ,  Arthur L. Spence ,  Gurjeet S. Saund ,  Robert P. Esser

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06F9/4893 ,  G06F9/52 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/08 ,  Y02D10/24

    Abstract: An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.

    Abstract translation: 系统的实施例可以包括多个媒体单元，处理器和电路。 每个媒体单元可以被配置为执行一个或多个命令来处理显示图像。 处理器可以被配置为在队列中存储多个媒体处理命令。 电路可以被配置为从队列检索第一媒体处理命令，并将第一媒体处理命令发送到第一媒体单元。 电路还可以被配置为响应于从第一媒体单元接收到中断而从队列中检索第二媒体处理并将第二媒体处理命令发送到第二媒体单元。 响应于接收到来自第一媒体单元的中断，电路可以将数据从第一媒体单元复制到第二媒体单元。

    Method and apparatus for arbitration with multiple source paths
    4.
    发明授权
    Method and apparatus for arbitration with multiple source paths 有权
    具有多个源路径仲裁的方法和装置

    公开(公告)号：US09189435B2

    公开(公告)日：2015-11-17

    申请号：US13868313

    申请日：2013-04-23

    Applicant: Apple Inc.

    Inventor： Benjamin K. Dodge ,  Deniz Balkan ,  Gurjeet S. Saund ,  Munetoshi Fukami

    IPC: G06F13/16 ,  G06F13/368

    CPC classification number: G06F13/368 ,  G06F13/16

    Abstract: A method and apparatus for arbitration. In one embodiment, a point in a network includes first and second arbiters. Arbitration of transactions associated with an address within a first range are conducted in the first arbiter, while arbitration of transactions associated with an address within a second range are conducted in the second arbiter. Each transaction is one of a number of different transaction types having a respective priority level. A measurement circuit is coupled to receive information from the first and second arbiters each cycle indicating the type of transactions that won their respective arbitrations. The measurement circuit may update a number of credits associated with the types of winning transactions. The updated number of credits may be provided to both the first and second arbiters, and may be used as a basis for arbitration in the next cycle.

    Abstract translation: 一种用于仲裁的方法和装置。 在一个实施例中，网络中的一个点包括第一和第二仲裁器。 与第一范围内的地址相关联的交易的仲裁在第一仲裁器中进行，而与第二范围内的地址相关联的交易的仲裁在第二仲裁器中进行。 每个事务是具有相应优先级的多个不同事务类型之一。 耦合测量电路以从第一和第二仲裁器接收信息，每个周期指示赢得其各自仲裁的交易类型。 测量电路可以更新与获胜交易的类型相关联的多个信用。 可以将更新的信用数量提供给第一和第二仲裁器，并且可以用作下一周期中的仲裁的基础。

    Bridge circuit for bus protocol conversion and error handling
    5.
    发明授权
    Bridge circuit for bus protocol conversion and error handling 有权
    用于总线协议转换和错误处理的桥接电路

    公开(公告)号：US09135202B2

    公开(公告)日：2015-09-15

    申请号：US13760795

    申请日：2013-02-06

    Applicant: Apple Inc.

    Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Shu-Yi Yu

    IPC: G06F13/40 ,  G06F11/07

    CPC classification number: G06F13/4027 ,  G06F11/0766 ,  G06F11/0772

    Abstract: Embodiments of a bridge circuit and system are disclosed that may allow for converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The bridge circuit may be configured to convert transactions from the first communication protocol to the second communication protocol, and convert transaction from the second communication protocol to the first communication protocol. In one embodiment, the bridge circuit may be further configured to flag transactions that cannot be converted from the second communication protocol to the first communication protocol. In a further embodiment, an error circuit coupled to the bridge circuit may be configured to detect flagged transactions.

    Abstract translation: 公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。 桥接电路可以被配置为将事务从第一通信协议转换为第二通信协议，并将事务从第二通信协议转换为第一通信协议。 在一个实施例中，桥接电路可以被进一步配置为标记不能从第二通信协议转换到第一通信协议的事务。 在另一个实施例中，耦合到桥接电路的错误电路可以被配置为检测标记的事务。

    CREDIT LOOKAHEAD MECHANISM
    6.
    发明申请
    CREDIT LOOKAHEAD MECHANISM 有权
    信用查询机制

    公开(公告)号：US20140181419A1

    公开(公告)日：2014-06-26

    申请号：US13724955

    申请日：2012-12-21

    Applicant: APPLE INC.

    Inventor： Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Benjamin K. Dodge

    IPC: G06F12/08

    CPC classification number: G06F13/385 ,  G06F13/28 ,  H04L47/10

    Abstract: Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if there are enough credits from the memory controller for forwarding the outstanding transactions stored in the IRQ. If there are not enough credits, then the coherence point prevents the switch fabric from forwarding additional transactions to the coherence point. By preventing excessive buffering in the IRQ, the QoS-based ordering of transactions performed by the switch fabric is preserved.

    Abstract translation: 在一致性点防止交易过度缓冲的系统和方法。 相干点使用前瞻机制来确定存储器控制器中是否有足够的信用来转发存储在IRQ中的未完成事务。 如果没有足够的积分，则相干点可以防止交换结构将附加事务转发到相干点。 通过防止IRQ中的过度缓冲，交换结构执行的事务的基于QoS的排序得以保留。

    PER-SOURCE ORDERING
    7.
    发明申请
    PER-SOURCE ORDERING 有权
    来源订单

    公开(公告)号：US20140181349A1

    公开(公告)日：2014-06-26

    申请号：US13724886

    申请日：2012-12-21

    Applicant: APPLE INC.

    Inventor： Deniz Balkan ,  Gurjeet S. Saund

    IPC: G06F13/16

    CPC classification number: G06F13/4027 ,  G06F13/4059 ,  G06F2213/0038

    Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge maintains a pair of counters for each source in a SoC to track the numbers of outstanding read and write transactions. The bridge prevents a read transaction from being forwarded to the second bus if the corresponding write counter is non-zero, and the bridge prevents a write transaction from being forwarded to the second bus if the corresponding read counter is non-zero.

    Abstract translation: 用于通过总线结构中的桥梁维护每个源的读取和写入事务顺序的系统和方法。 该桥提供从总线结构中的第一总线到第二总线的连接。 第一个总线具有读取和写入事务的单一路径，第二个总线具有用于读取和写入事务的独立路径。 该桥在SoC中为每个源保留一对计数器，以跟踪未完成的读写事务的数量。 如果相应的写计数器不为零，桥将阻止读事务被转发到第二总线，如果相应的读计数器不为零，桥将阻止写事务被转发到第二总线。

    Dynamic Clock and Power Gating with Decentralized Wake-Ups
    8.
    发明申请
    Dynamic Clock and Power Gating with Decentralized Wake-Ups 有权
    具有分散唤醒功能的动态时钟和电源门控

    公开(公告)号：US20140167840A1

    公开(公告)日：2014-06-19

    申请号：US13719517

    申请日：2012-12-19

    Applicant: APPLE INC.

    Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil

    IPC: G05B11/01

    CPC classification number: G05B11/01 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

    Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

    Abstract translation: 公开了一种用于动态时钟和电源门控和分散式唤醒的方法和装置。 在一个实施例中，集成电路（IC）包括功率可管理的功能单元和电源管理单元。 每个功率可管理功能单元被配置为向电力管理单元传送进入低功率状态的请求。 功率管理单元可以通过使请求功能单元进入低功率状态来进行响应。 如果另一个功能单元发起与当前处于低功率状态的功能单元通信的请求，则它可以向该功能单元发送请求。 接收功能单元可以通过退出低功率状态并在活动状态下恢复运行来响应该请求。

    Media Compositor For Computer-Generated Reality
    9.
    发明申请
    Media Compositor For Computer-Generated Reality 审中-公开

    公开(公告)号：US20200043237A1

    公开(公告)日：2020-02-06

    申请号：US16533053

    申请日：2019-08-06

    Applicant: Apple Inc.

    Inventor： Ranjit Desai ,  Venu M. Duggineni ,  Perry A. Caro ,  Aleksandr M. Movshovich ,  Gurjeet S. Saund

    IPC: G06T19/00 ,  G10L25/51 ,  G06F3/01 ,  G06T9/00 ,  G06T3/00 ,  H04L29/06

    Abstract: One implementation forms a composited stream of computer-generated reality (CGR) content using multiple data streams related to a CGR experience to facilitate recording or streaming. A media compositor obtains a first data stream of rendered frames and a second data stream of additional data. The rendered frame content (e.g., 3D models) represents real and virtual content rendered during a CGR experience at a plurality of instants in time. The additional data of the second data stream relates to the CGR experience, for example, relating to audio, audio sources, metadata identifying detected attributes of the CGR experience, image data, data from other devices involved in the CGR experience, etc. The media compositor forms a composited stream that aligns the rendered frame content with the additional data for the plurality of instants in time, for example, by forming time-stamped, n-dimensional datasets (e.g., images) corresponding to individual instants in time.

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