Syndrome Weight Based Evaluation of Memory Cells Performance Using Multiple Sense Operations

    公开(公告)号:US20190035485A1

    公开(公告)日:2019-01-31

    申请号:US15658430

    申请日:2017-07-25

    Applicant: Apple Inc.

    CPC classification number: G11C29/42 G06F11/1012 G06F11/1076 G11C29/44

    Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to read from a group of the memory cells a code word encoded using an Error Correction Code (ECC), by sensing the memory cells using at least first and second read thresholds for producing respective first and second readouts, to calculate, based on at least one of the first and second readouts, (i) a syndrome weight that is indicative of an actual number of errors contained in the code word, and (ii) a mid-zone count of the memory cells for which the first readout differs from the second readout, and, to evaluate a performance measure for the memory cells, based on the calculated syndrome weight and mid-zone count.

    DATA ENCODING BY EFFICIENT INVERSION OF A PARITY-CHECK SUB-MATRIX
    2.
    发明申请
    DATA ENCODING BY EFFICIENT INVERSION OF A PARITY-CHECK SUB-MATRIX 审中-公开
    通过有效反转的奇偶校验子矩阵的数据编码

    公开(公告)号:US20170047948A1

    公开(公告)日:2017-02-16

    申请号:US14823061

    申请日:2015-08-11

    Applicant: APPLE INC.

    CPC classification number: H03M13/616 H03M13/116 H03M13/611 H03M13/6502

    Abstract: A method for data encoding includes receiving a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H. An intermediate vector s is produced by multiplying the data vector by a data sub-matrix Hs of the parity-check matrix H. A parity part of the code word is derived by applying a sequence of operations to the intermediate vector s based on a decomposition of a parity sub-matrix Hp of the matrix H using matrices A, C, U and V, in which decomposition A is a block triangular matrix that has the same size as Hp, C is matrix that is smaller than Hp, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation Hp=A+UCV.

    Abstract translation: 一种用于数据编码的方法包括:根据由奇偶校验矩阵H定义的代码,将要编码的数据向量接收到码字中。通过将数据矢量乘以数据子矩阵Hs 奇偶校验矩阵H.通过基于使用矩阵A,C,U的矩阵H的奇偶校验子矩阵Hp的分解,向中间向量s应用一系列操作来导出码字的奇偶校验部分, V,其中分解A是具有与Hp相同大小的块三角矩阵,C是小于Hp的矩阵,矩阵U和V是选择为使得A,C,U和V满足的放置​​矩阵 矩阵方程Hp = A + UCV。

    Decoder with selective iteration scheduling
    3.
    发明授权
    Decoder with selective iteration scheduling 有权
    具有选择性迭代调度的解码器

    公开(公告)号:US09258015B2

    公开(公告)日:2016-02-09

    申请号:US14138809

    申请日:2013-12-23

    Applicant: Apple Inc.

    CPC classification number: H03M13/1111 H03M13/1128 H03M13/114 H03M13/3715

    Abstract: A method includes decoding a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations, such that each iteration involves processing of multiple variable nodes. For one or more selected variable nodes, a count of the check equations that are defined over one or more variables held respectively by the one or more selected variable nodes is evaluated, and, when the count meets a predefined skipping criterion, the one or more selected variable nodes are omitted from a given iteration in the sequence.

    Abstract translation: 一种方法包括通过执行一系列迭代来解码纠错码(ECC)的代码字,其可由一组检验方程表示,使得每次迭代涉及多个可变节点的处理。 对于一个或多个选定的变量节点,评估在一个或多个所选变量节点分别保存的一个或多个变量上定义的检验方程的计数,并且当该计数满足预定的跳过标准时,该一个或多个 在序列中给定的迭代中省略了选定的变量节点。

    Signal-to-Noise Ratio (SNR) estimation in analog memory cells based on optimal read thresholds
    4.
    发明授权
    Signal-to-Noise Ratio (SNR) estimation in analog memory cells based on optimal read thresholds 有权
    基于最佳读取阈值的模拟存储器单元中的信噪比(SNR)估计

    公开(公告)号:US09136001B2

    公开(公告)日:2015-09-15

    申请号:US13657150

    申请日:2012-10-22

    Applicant: Apple Inc.

    CPC classification number: G11C11/5642 G11C16/08 G11C16/10 G11C16/20 G11C16/26

    Abstract: A method includes programming a group of analog memory cells by writing respective analog values into the memory cells in the group. After programming the group, the analog values are read from the memory cells in the group using a set of read thresholds so as to produce readout results. Respective optimal positions for the read thresholds in the set are identified based on the readout results. A noise level in the readout results is estimated based on the identified optimal positions of the read thresholds.

    Abstract translation: 一种方法包括通过将相应的模拟值写入组中的存储器单元来对一组模拟存储器单元进行编程。 在对该组进行编程之后,使用一组读取阈值从组中的存储器单元读取模拟值,以产生读出结果。 基于读出结果来识别集合中读取阈值的各个最佳位置。 基于所识别的读取阈值的最佳位置来估计读出结果中的噪声电平。

    Sign equalization in iterative decoding of sparse graph codes
    5.
    发明授权
    Sign equalization in iterative decoding of sparse graph codes 有权
    稀疏图代码的迭代解码中的符号均衡

    公开(公告)号:US08862959B1

    公开(公告)日:2014-10-14

    申请号:US13747559

    申请日:2013-01-23

    Applicant: Apple Inc.

    Abstract: A method includes, in an Error Correction Code (ECC) decoder that includes variable nodes and check nodes, receiving in a given variable node Check-to-Variable (C2V) messages from a subset of the check nodes. Magnitudes for respective Variable-to-Check (V2C) messages to be sent to the check nodes in the subset are computed based on the received C2V messages. A single sign is computed, for use in all the V2C messages to be sent from the given variable node to the check nodes in the subset. The V2C messages are sent from the given variable node to the check nodes in the subset, such that each V2C message includes a respective magnitude and the single sign.

    Abstract translation: 一种方法包括在包括变量节点和校验节点的纠错码(ECC)解码器中,从给定的变量节点接收来自校验节点的子集的“一对一变量”(C2V)消息。 基于接收到的C2V消息计算要发送到子集中的校验节点的相应可变检查(V2C)消息的幅度。 计算单个符号,用于从给定变量节点发送到子集中的校验节点的所有V2C消息。 V2C消息从给定的变量节点发送到子集中的校验节点,使得每个V2C消息包括相应的大小和单个符号。

    Efficient LDPC decoding with predefined iteration-dependent scheduling scheme

    公开(公告)号:US10389388B2

    公开(公告)日:2019-08-20

    申请号:US15856107

    申请日:2017-12-28

    Applicant: Apple Inc.

    Abstract: A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.

    EFFICIENT CODING WITH SINGLE-ERROR CORRECTION AND DOUBLE-ERROR DETECTION CAPABILITIES

    公开(公告)号:US20170111061A1

    公开(公告)日:2017-04-20

    申请号:US14883657

    申请日:2015-10-15

    Applicant: APPLE INC.

    Abstract: An apparatus for data coding includes an encoder and a decoder. The encoder is configured to receive input data including one or more m-bit data groups that are associated with respective group indices, to generate a code word that includes the input data and an m-bit redundancy that depends on the data groups and on the respective group indices, and to send the code word over a channel. The decoder is connected to the channel and is configured to produce a syndrome that equals zero when the code word is error-free, and when the code word contains a single error caused by the channel, is indicative of an erroneous group in which the single error occurred, and of a location of the single error within the erroneous group, and to recover the input data by correcting the single error at the location in the erroneous group.

    LDPC decoder with efficient circular shifters
    8.
    发明授权
    LDPC decoder with efficient circular shifters 有权
    具有高效圆形移位器的LDPC解码器

    公开(公告)号:US09595977B2

    公开(公告)日:2017-03-14

    申请号:US14499284

    申请日:2014-09-29

    Applicant: APPLE INC.

    Abstract: A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.

    Abstract translation: 解码器包括可变节点电路,校验节点电路和消息传递(MP)模块,消息传递(MP)模块包括多个可配置的部分循环移位器,每个移位器仅支持移位值0的全范围内的移位值的部分子集。 。 。 L-1。 可变节点电路和校验节点电路被配置为根据表示相应的准循环(QC) - 低密度奇偶校验(LDPC)纠错码(ECC)的奇偶校验矩阵和彼此之间的交换消息 其包括L乘L子矩阵,并处理所交换的消息以解码使用QC-LDPC ECC编码的给定码字。 MP模块被配置为根据相应的子矩阵来调度互连的可变节点电路和校验节点电路,以通过分配给定的部分循环移位器来周期性地移动L个消息来同时交换L个消息 这取决于相应子矩阵的结构。

    CORRECTING SOFT RELIABILITY MEASURES OF STORAGE VALUES READ FROM MEMORY CELLS
    9.
    发明申请
    CORRECTING SOFT RELIABILITY MEASURES OF STORAGE VALUES READ FROM MEMORY CELLS 有权
    从存储单元读取存储值的软可靠性措施

    公开(公告)号:US20160092301A1

    公开(公告)日:2016-03-31

    申请号:US14499207

    申请日:2014-09-28

    Applicant: Apple Inc.

    CPC classification number: G06F11/1068 G06F11/1012 G11C29/52 H03M13/45

    Abstract: A method for data storage includes reading storage values, which represent stored data, from a group of memory cells using read thresholds, and deriving respective soft reliability metrics for the storage values. The storage values are classified into two or more subgroups based on a predefined classification criterion. Independently within each subgroup, a subgroup-specific distribution of the storage values in the subgroup is estimated, and the soft reliability metrics of the storage values in the subgroup are corrected based on the subgroup-specific distribution. The stored data is decoded using the corrected soft reliability metrics.

    Abstract translation: 一种用于数据存储的方法包括:使用读取阈值从一组存储器单元读取表示存储数据的存储值,以及导出用于存储值的相应的软可靠性度量。 基于预定义的分类标准将存储值分类为两个或更多个子组。 在每个子组内独立地估计子组中存储值的子组特定分布,并且基于子组特定分布来校正子组中的存储值的软可靠性度量。 使用校正的软可靠性度量对存储的数据进行解码。

    Soft message-passing decoder with efficient message computation
    10.
    发明授权
    Soft message-passing decoder with efficient message computation 有权
    软消息传递解码器,有效的消息计算

    公开(公告)号:US08914710B2

    公开(公告)日:2014-12-16

    申请号:US13628321

    申请日:2012-09-27

    Applicant: Apple Inc.

    Abstract: A method includes, in a decoder of an Error Correction Code (ECC), maintaining only aggregated information regarding a set of messages, a function of which is to be reported from a first node to a second node of the decoder. The function of the set is determined and reported using the aggregated information. After reporting the function, one of the messages in the set is replaced with a new message. The aggregated information is updated to reflect the set having the new message, and the function of the set having the new message is determined and reported using the updated aggregated information.

    Abstract translation: 一种方法包括在纠错码(ECC)的解码器中维护关于一组消息的聚合信息,其功能将从解码器的第一节点报告给第二节点。 使用聚合信息确定并报告集合的功能。 报告功能后,集合中的消息之一将被替换为新消息。 聚合信息被更新以反映具有新消息的集合,并且使用更新的聚合信息确定并报告具有新消息的集合的功能。

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