公开(公告)号：US20190066814A1

公开(公告)日：2019-02-28

申请号：US15684239

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Renu Rawat ,  Paul Darren Hoxey ,  Vikash ,  Kumaraswamy Ramanathan ,  Sanjay Mangal ,  Yew Keong Chong

IPC: G11C29/12 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C29/1201 ,  G11C5/066 ,  G11C7/1018 ,  G11C7/1036 ,  G11C11/418 ,  G11C11/419 ,  G11C29/12015 ,  G11C29/32 ,  G11C2029/1204 ,  G11C2207/107

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

公开(公告)号：US10741227B2

公开(公告)日：2020-08-11

申请号：US16058375

申请日：2018-08-08

Applicant: Arm Limited

Inventor： Kumaraswamy Ramanathan ,  Peixuan Tan ,  Andy Wangkun Chen

IPC: G11C8/00 ,  G11C7/22 ,  H03K3/037

Abstract: Various implementations described herein refer to an integrated circuit having a first pulse generator and a second pulse generator. The first pulse generator generates a first clock pulse for a two pulse sequence based on one or more input signals. The second pulse generator is coupled to the first pulse generator and generates a second clock pulse for the two pulse sequence based on the one or more input signals. The second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.

公开(公告)号：US20200051602A1

公开(公告)日：2020-02-13

申请号：US16058375

申请日：2018-08-08

Applicant: Arm Limited

Inventor： Kumaraswamy Ramanathan ,  Peixuan Tan ,  Andy Wangkun Chen

IPC: G11C7/22 ,  H03K3/037

Abstract: Various implementations described herein refer to an integrated circuit having a first pulse generator and a second pulse generator. The first pulse generator generates a first clock pulse for a two pulse sequence based on one or more input signals. The second pulse generator is coupled to the first pulse generator and generates a second clock pulse for the two pulse sequence based on the one or more input signals. The second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.

公开(公告)号：US11514979B2

公开(公告)日：2022-11-29

申请号：US17218949

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Munish Kumar ,  Ayush Kulshrestha ,  Rajiv Kumar Sisodia ,  Yew Keong Chong ,  Kumaraswamy Ramanathan ,  Edward Martin McCombs, Jr.

IPC: G11C8/00 ,  G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.

公开(公告)号：US20200066365A1

公开(公告)日：2020-02-27

申请号：US16666164

申请日：2019-10-28

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Renu Rawat ,  Paul Darren Hoxey ,  Vikash ,  Kumaraswamy Ramanathan ,  Sanjay Mangal ,  Yew Keong Chong

IPC: G11C29/12 ,  G11C11/419 ,  G11C11/418 ,  G11C29/32 ,  G11C7/10

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

公开(公告)号：US10460822B2

公开(公告)日：2019-10-29

申请号：US15684239

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Renu Rawat ,  Paul Darren Hoxey ,  Vikash ,  Kumaraswamy Ramanathan ,  Sanjay Mangal ,  Yew Keong Chong

IPC: G11C29/12 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C29/32 ,  G11C5/06

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

公开(公告)号：US20220319585A1

公开(公告)日：2022-10-06

申请号：US17218949

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Munish Kumar ,  Ayush Kulshrestha ,  Rajiv Kumar Sisodia ,  Yew Keong Chong ,  Kumaraswamy Ramanathan ,  Edward Martin McCombs, JR.

IPC: G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.

公开(公告)号：US10665591B2

公开(公告)日：2020-05-26

申请号：US16122752

申请日：2018-09-05

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Kumaraswamy Ramanathan ,  Damayanti Datta

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  G11C11/40 ,  H03K3/012

Abstract: Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.

公开(公告)号：US20200075591A1

公开(公告)日：2020-03-05

申请号：US16122752

申请日：2018-09-05

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Kumaraswamy Ramanathan ,  Damayanti Datta

IPC: H01L27/092 ,  H01L29/78 ,  H03K3/012 ,  G11C11/40 ,  H01L21/8238

Abstract: Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.

公开(公告)号：US11145651B2

公开(公告)日：2021-10-12

申请号：US16882634

申请日：2020-05-25

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Kumaraswamy Ramanathan ,  Damayanti Datta

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  G11C11/40 ,  H03K3/012

Abstract: Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.