公开(公告)号：US20230220588A1

公开(公告)日：2023-07-13

申请号：US18153254

申请日：2023-01-11

Applicant: ASM IP Holding B.V.

Inventor： Steven Van Aerde ,  Wilco Verweij ,  Dieter Pierreux ,  Kelly Houben ,  Bert Jongbloed ,  Peter Westrom

IPC: C30B29/68 ,  H01L21/677 ,  H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52

CPC classification number: C30B29/68 ,  H01L21/67742 ,  H01L21/02532 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/0262 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02433

Abstract: A method of forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing a semiconductor processing apparatus. This semiconductor processing apparatus comprises a process chamber and a carousel for stationing a wafer boat before or after processing in the process chamber. The method further comprises loading the wafer boat into the process chamber, the wafer boat comprising the plurality of substrates. The method further comprises processing the plurality of substrates in the process chamber, thereby forming, on the plurality of substrates, the epitaxial stack. This epitaxial stack has a pre-determined thickness. The processing comprises unloading the wafer boat, one or more times, from the process chamber to the carousel until the epitaxial stack reaches the pre-determined thickness.

公开(公告)号：US20250079159A1

公开(公告)日：2025-03-06

申请号：US18815701

申请日：2024-08-26

Applicant: ASM IP Holding, B.V.

Inventor： Dieter Pierreux ,  Steven Van Aerde ,  Kelly Houben ,  Bert Jongbloed

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/455

Abstract: The technology of the present disclosure generally relates to the field of semiconductor devices. More particularly, semiconductor structures, systems, and methods for producing the same, comprising surface-modified silicon layers formed by reacting a deposited silicon layer with a halide reactant. The system comprising one or more reaction chamber constructed and arranged to hold a substrate; a silicon precursor vessel constructed and arranged to contain and evaporate a silicon precursor; a halide reactant vessel constructed and arranged to contain and evaporate a halide reactant; an exhaust source; and a controller; wherein the controller is configured to control the flow of said silicon precursor and said halide reactant into said reaction chamber, thereby forming a surface-modified silicon layer on said substrate.

公开(公告)号：US20240339359A1

公开(公告)日：2024-10-10

申请号：US18626758

申请日：2024-04-04

Applicant: ASM IP Holding B.V.

Inventor： René Henricus Jozef Vervuurt ,  Timothee Blanquart ,  Jihee Jeon ,  YongMin Yoo ,  Andrey Sokolov ,  Maarten Stokhof ,  Steven Van Aerde ,  Dieter Pierreux ,  Hussein Mehdi

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/02274

Abstract: The present disclosure relates to method and apparatuses for filling a gap on a substrate. The method comprises providing a substrate, which comprises at least one gap into a reaction chamber, depositing a silicon containing first layer onto the substrate; subjecting the first layer to a phosphorous containing compound to form a flowable intermediate material, which at least partially fills the at least one gap on the substrate; and forming a solid material comprising silicon.

公开(公告)号：US20230223255A1

公开(公告)日：2023-07-13

申请号：US18153272

申请日：2023-01-11

Applicant: ASM IP Holding, B.V.

Inventor： Steven Van Aerde ,  Wilco Verweij ,  Bert Jongbloed ,  Dieter Pierreux ,  Kelly Houben ,  Rami Khazaka ,  Frederick Aryeetey ,  Peter Westrom ,  Omar Elleuch ,  Caleb Miskin

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68

CPC classification number: H01L21/0257 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/0262 ,  H01L21/02532

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.

公开(公告)号：US11230766B2

公开(公告)日：2022-01-25

申请号：US15940729

申请日：2018-03-29

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Cornelis Thaddeus Herbschleb ,  Werner Knaepen ,  Bert Jongbloed ,  Steven Van Aerde ,  Kelly Houben ,  Theodorus Oosterlaken ,  Chris de Ridder ,  Lucian Jdira

IPC: C23C16/458 ,  C23C16/56 ,  C23C16/455 ,  C23C16/48 ,  C23C16/50 ,  C23C16/44

Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.

公开(公告)号：US20190301014A1

公开(公告)日：2019-10-03

申请号：US15940729

申请日：2018-03-29

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Cornelis Thaddeus Herbschleb ,  Werner Knaepen ,  Bert Jongbloed ,  Steven Van Aerde ,  Kelly Houben ,  Theodorus Oosterlaken ,  Chris de Ridder ,  Lucian Jdira

IPC: C23C16/458 ,  C23C16/56 ,  C23C16/50 ,  C23C16/48 ,  C23C16/455

Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.

公开(公告)号：US20230223258A1

公开(公告)日：2023-07-13

申请号：US18153282

申请日：2023-01-11

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Kelly Houben ,  Steven Van Aerde ,  Wilco Verweij ,  Bert Jongbloed ,  Charles Dezelah

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  C30B25/18

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L21/02661 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  C30B25/186

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer and the second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer

公开(公告)号：US20230127833A1

公开(公告)日：2023-04-27

申请号：US18048188

申请日：2022-10-20

Applicant: ASM IP Holding B.V.

Inventor： Steven Van Aerde ,  Juan Su

IPC: H01L21/02

Abstract: A method and a wafer processing furnace for forming a doped polysilicon layer on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing a plurality of substrates to a process chamber. It also comprises executing a deposition cycle comprising providing a silicon-containing precursor to the process chamber thereby depositing, on the plurality of substrates, an undoped silicon layer until a pre-determined thickness is reached and providing the process chamber with a flow of a dopant precursor gas without providing the silicon-containing precursor to the process chamber. The method also comprises performing a heat treatment process, thereby forming the doped polysilicon layer.