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    BUFFER DISPLAY DATA IN A CHIPLET ARCHITECTURE
    2.
    发明公开
    BUFFER DISPLAY DATA IN A CHIPLET ARCHITECTURE 审中-公开

    公开(公告)号：US20240211023A1

    公开(公告)日：2024-06-27

    申请号：US18146811

    申请日：2022-12-27

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Gia Tung Phan ,  Ashish Jain ,  Shang Yang

    IPC: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60

    CPC classification number: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/45

    Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

    ADAPTIVE POWER THROTTLING SYSTEM
    4.
    发明公开
    ADAPTIVE POWER THROTTLING SYSTEM 审中-公开

    公开(公告)号：US20240004725A1

    公开(公告)日：2024-01-04

    申请号：US17854650

    申请日：2022-06-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Shang Yang ,  Arash Moghimi

    IPC: G06F9/50

    CPC classification number: G06F9/5094 ,  G06F9/505 ,  G06F9/5038

    Abstract: Systems, apparatuses, and methods for managing power allocation in a computing system. A system management unit detects a condition indicating a change in power is indicated. Such a change may be detecting an indication that a power change is either required, possible, or requested. In response to detecting a reduction in power is indicated, the system management unit identifies currently executing tasks of the computing system and accesses sensitivity data to determine which of a number of computing units (or power domains) to select for power reduction. Based at least in part on the data, a unit is identified that is determined to have a relatively low sensitivity to power state changes under the current operating conditions. A relatively low sensitivity indicates that a change in power to the corresponding unit will not have as significant an impact on overall performance of the computing system than if another unit was selected. Power allocated for the selected unit is then decreased.

    TRUSTED PROCESSOR FOR SAVING GPU CONTEXT TO SYSTEM MEMORY
    5.
    发明申请
    TRUSTED PROCESSOR FOR SAVING GPU CONTEXT TO SYSTEM MEMORY 有权

    公开(公告)号：US20220414222A1

    公开(公告)日：2022-12-29

    申请号：US17356776

    申请日：2021-06-24

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Gia Phan ,  Ashish Jain ,  Randall Brown

    IPC: G06F21/57 ,  G06F21/60 ,  G06F9/46 ,  G06F9/50 ,  G06T1/20

    Abstract: A trusted processor saves and restores context and data stored at a frame buffer of a GPU concurrent with initialization of a CPU of the processing system. In response to detecting that the GPU is powering down, the trusted processor accesses the context of the GPU and data stored at a frame buffer of the GPU via a high-speed bus. The trusted processor stores the context and data at a system memory, which maintains the context and data while the GPU is powered down. In response to detecting that the GPU is powering up again, the trusted processor restores the context and data to the GPU, which can be performed concurrently with initialization of the CPU.

    BOOSTING THE OPERATING POINT OF A PROCESSING DEVICE FOR NEW USER ACTIVITIES
    6.
    发明申请
    BOOSTING THE OPERATING POINT OF A PROCESSING DEVICE FOR NEW USER ACTIVITIES 审中-公开
    促进新用户活动的处理设备的操作要点

    公开(公告)号：US20150193259A1

    公开(公告)日：2015-07-09

    申请号：US14147470

    申请日：2014-01-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Alexander J. Branover

    IPC: G06F9/46

    CPC classification number: G06F9/4893 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/24

    Abstract: A processing system detects user activities on one or more processing units. In response, an operating point (operating frequency or an operating voltage) of the processing unit handing the user activity is increased at the processing unit. Battery power may be conserved in some processing systems by limiting the increase in the operating point to a time interval and reducing the operating frequency or the operating voltage to a previous value after the time interval has elapsed.

    Abstract translation: 处理系统检测一个或多个处理单元上的用户活动。 作为响应，在处理单元处增加处理单元处理用户活动的操作点（操作频率或工作电压）。 在一些处理系统中，通过将工作点的增加限制到时间间隔并且在经过时间间隔之后将工作频率或工作电压降低到先前值，可以节省电池功率。

    METHOD AND APPARATUS TO MIGRATE MORE SENSITIVE WORKLOADS TO FASTER CHIPLETS
    7.
    发明申请
    METHOD AND APPARATUS TO MIGRATE MORE SENSITIVE WORKLOADS TO FASTER CHIPLETS 有权

    公开(公告)号：US20240419481A1

    公开(公告)日：2024-12-19

    申请号：US18334363

    申请日：2023-06-13

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Ashkan Hosseinzadeh Namin

    IPC: G06F9/46

    Abstract: An apparatus and method for efficiently performance among replicated functional blocks of an integrated circuit despite different circuit behavior amongst the functional blocks due to manufacturing variations. An integrated circuit includes multiple replicated functional blocks, each being a semiconductor die with an instantiated copy of particular integrated circuitry for processing a work block. One or more of the functional blocks of the integrated circuit belong in a different performance category or bin than other functional blocks due to manufacturing variations across semiconductor dies. A scheduler assigns work blocks to the functional blocks based on whether a functional block is from a high-performance bin and whether a workload of a work block is a computation intensive workload. The scheduler assigns work blocks work blocks marked as having a memory access intensive workload to functional blocks from a lower performance bin.

    BALANCED THROUGHPUT OF REPLICATED PARTITIONS IN PRESENCE OF INOPERABLE COMPUTATIONAL UNITS
    9.
    发明公开
    BALANCED THROUGHPUT OF REPLICATED PARTITIONS IN PRESENCE OF INOPERABLE COMPUTATIONAL UNITS 审中-公开

    公开(公告)号：US20230409392A1

    公开(公告)日：2023-12-21

    申请号：US17844558

    申请日：2022-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Sriram Sundaram ,  Christopher Allan Poirier ,  Samuel D. Naffziger

    IPC: G06F9/48 ,  G06F1/26

    CPC classification number: G06F9/4893 ,  G06F1/26

    Abstract: An apparatus and method for efficiently managing balanced performance among replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects. A processing unit includes at least two replicated partitions, each assigned to operation parameters of a respective power domain. The partitions include multiple compute units. The compute units include multiple lanes of execution. Due to a variety of types of manufacturing defects, one or more of the partitions of the processing unit has less than a predetermined number of operational compute units. To balance the throughput of the multiple partitions, a power manager generates both static and dynamic scaling factors based on at least the corresponding number of operational compute units. Using these scaling factors, the power manager adjusts the operation parameters of power domains for the partitions relative to one another.

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