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    CLOCK FREQUENCY DIVIDER CIRCUIT
    1.
    发明申请
    CLOCK FREQUENCY DIVIDER CIRCUIT 有权

    公开(公告)号：US20230136815A1

    公开(公告)日：2023-05-04

    申请号：US17514723

    申请日：2021-10-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Luke Jereme Whitaker ,  Edoardo Prete

    IPC: G06F1/08 ,  H03K23/00 ,  H03K17/693

    Abstract: A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.

    INTEGRATED CONTROLLER FOR TRAINING MEMORY PHYSICAL LAYER INTERFACE
    4.
    发明申请
    INTEGRATED CONTROLLER FOR TRAINING MEMORY PHYSICAL LAYER INTERFACE 有权
    用于训练存储器物理层接口的集成控制器

    公开(公告)号：US20150378603A1

    公开(公告)日：2015-12-31

    申请号：US14318114

    申请日：2014-06-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Glenn A. Dearth ,  Gerry Talbot ,  Anwar Kashem ,  Edoardo Prete ,  Brian Amick

    IPC: G06F3/06

    CPC classification number: G06F13/4072 ,  G06F13/1689

    Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

    Abstract translation: 集成在存储器物理层接口（PHY）中的控制器可用于控制用于配置存储器PHY的训练以与诸如动态随机存取存储器（DRAM）的相关联的外部存储器进行通信，由此消除提供训练序列的需要 在BIOS和存储器PHY之间的数据流水线上。 例如，集成在存储器PHY中的控制器可以基于训练算法来控制用于与外部存储器通信的存储器PHY的读取训练和写入训练。 训练算法可以是无核训练算法，其收敛于存储器PHY和外部存储器之间的定时延迟和电压偏移的解，而不从基本输入/输出系统（BIOS）接收表征信号的种子信息 由训练序列生成的训练序列或命令所遍历的路径。

    MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE
    5.
    发明申请
    MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE 审中-公开
    用于分割通道架构的记忆系统组件

    公开(公告)号：US20140325105A1

    公开(公告)日：2014-10-30

    申请号：US13871437

    申请日：2013-04-26

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Edoardo Prete ,  Anwar Kashem ,  Brian Amick

    IPC: H01L23/538 ,  G06F13/16

    CPC classification number: G06F13/1642

    Abstract: In one form, a memory module includes a first plurality of memory devices comprising a first rank and having a first group and a second group, and first and second chip select conductors. The first chip select conductor interconnects chip select input terminals of each memory device of the first group, and the second chip select conductor interconnects chip select input terminals of each memory device of the second group. In another form, a system includes a memory controller that performs a first burst access using both first and second portions of a data bus and first and second chip select signals in response to a first access request, and a second burst access using a selected one of the first and second portions of the data bus and a corresponding one of the first and second chip select signals in response to a second access request.

    Abstract translation: 在一种形式中，存储器模块包括包括第一等级并具有第一组和第二组以及第一和第二芯片选择导体的第一多个存储器件。 第一芯片选择导体互连第一组的每个存储器件的芯片选择输入端，并且第二芯片选择导体互连第二组的每个存储器件的芯片选择输入端。 在另一种形式中，系统包括存储器控制器，其响应于第一访问请求，使用数据总线的第一和第二部分以及第一和第二片选信号执行第一突发存取，并且使用所选择的一个进行第二突发存取 的数据总线的第一和第二部分以及响应于第二访问请求的第一和第二片选信号中的对应的一个。

    Periodic receiver clock data recovery with dynamic data edge
    6.
    发明授权
    Periodic receiver clock data recovery with dynamic data edge 有权

    公开(公告)号：US12174769B2

    公开(公告)日：2024-12-24

    申请号：US17705048

    申请日：2022-03-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gurunath Dollin ,  Edoardo Prete ,  Milam Paraschou ,  Edward Wade Thoenes ,  Ryan J. Hensley ,  Gerald R. Talbot

    IPC: G06F13/40 ,  G06F1/08 ,  G06F1/12 ,  G06F13/42 ,  H03K19/173

    Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.

    Common mode extraction and tracking for data signaling
    7.
    发明授权
    Common mode extraction and tracking for data signaling 有权

    公开(公告)号：US09673849B1

    公开(公告)日：2017-06-06

    申请号：US15237754

    申请日：2016-08-16

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Milam Paraschou ,  Edoardo Prete

    IPC: H04B1/10 ,  H04B1/76 ,  H04B15/00

    CPC classification number: H04B1/10 ,  H04B1/76 ,  H04B3/32 ,  H04B15/00

    Abstract: Systems, apparatuses, and methods for performing common mode extraction for data communication are disclosed. A circuit is configured to receive a single-ended data signal on a first input port and couple the data signal to a positive input terminal of a receiver component. The circuit is also configured to receive a differential clock signal on second and third input ports and generate a reference signal from the differential clock signal. In one embodiment, the reference signal is generated from an average of the differential clock signal. The circuit is configured to couple the reference signal to a negative input terminal of the receiver component. In one embodiment, the receiver component is an amplifier.

    Integrated controller for training memory physical layer interface
    8.
    发明授权
    Integrated controller for training memory physical layer interface 有权

    公开(公告)号：US09639495B2

    公开(公告)日：2017-05-02

    申请号：US14318114

    申请日：2014-06-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Glenn A. Dearth ,  Gerry Talbot ,  Anwar Kashem ,  Edoardo Prete ,  Brian Amick

    IPC: G06F12/00 ,  G06F13/40

    CPC classification number: G06F13/4072 ,  G06F13/1689

    Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

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