公开(公告)号：US20240321702A1

公开(公告)日：2024-09-26

申请号：US18474166

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Yan Wang ,  Kevin Gillespie ,  Samuel Naffziger ,  Richard Schultz ,  Raja Swaminathan ,  Omar Zia ,  John Wuu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/3675 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/32146 ,  H01L2224/32165 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/351

Abstract: A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240321827A1

公开(公告)日：2024-09-26

申请号：US18474158

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Omar Zia ,  Thomas D Burd ,  Kevin Gillespie ,  Samuel Naffziger ,  Richard Schultz ,  Raja Swaminathan ,  Srividhya Venkataraman ,  Yan Wang ,  John Wuu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/36 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can also include connecting the first metal stack to the second metal stack. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240321668A1

公开(公告)日：2024-09-26

申请号：US18474138

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Thomas D. Burd ,  Gabriel H. Loh ,  John Wuu ,  Kevin Gillespie ,  Raja Swaminathan ,  Richard Schultz ,  Samuel Naffziger ,  Srividhya Venkataraman ,  Yan Wang

IPC: H01L23/34 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/34 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16225 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1437

Abstract: A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11652050B2

公开(公告)日：2023-05-16

申请号：US17135122

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Richard Schultz

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/45

CPC classification number: H01L23/5286 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/45

Abstract: A cell layout implemented in an integrated circuit (IC) includes a first plurality of independent power posts in a first metal layer. Each independent power post of the plurality of independent power posts provides a power connection to one device of a plurality of devices within the cell layout. A source or drain of each device of the plurality of devices is connected to one independent power post of the plurality of independent power posts. The IC further includes a plurality of independent power straps in a second metal layer that is different from the first metal layer. Each independent power strap of the plurality of independent power straps spans across and connects to multiple independent power posts of the first plurality of independent power posts.

公开(公告)号：US11004791B2

公开(公告)日：2021-05-11

申请号：US16382774

申请日：2019-04-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Richard Schultz

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.

公开(公告)号：US20240403529A1

公开(公告)日：2024-12-05

申请号：US18326835

申请日：2023-05-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Richard Schultz ,  Omid Rowhani

IPC: G06F30/392 ,  G06F30/394 ,  H01L27/118

Abstract: An apparatus and method for efficiently creating layout of standard cells to improve floor planning of a chip. In various implementations, an integrated circuit uses multiple standard cells with an absence of diffusion breaks at cell boundaries. The standard cells use vertically stacked non-planer transistors. Multiple transistors are formed with an active region having a length between a source region and a drain region of a single transistor. Therefore, the active regions of these transistors are not formed across multiple gate terminals. By having active regions of these transistors formed across a single gate terminal of a single transistor, there is sufficient spacing to provide electrical isolation between two active regions of the two adjoining standard cells. This is true even when the two adjoining standard cells share a source/drain region at the cell boundaries. Accordingly, forming diffusion breaks at the edges of these standard cells can be skipped.

公开(公告)号：US20240145565A1

公开(公告)日：2024-05-02

申请号：US17974643

申请日：2022-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard Schultz

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/1025

Abstract: The disclosed integrated circuit for offset cross field effect transistors can include a first transistor include a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; and a second transistor adjacent to the oxide layer. The second transistor can include a second channel that is oriented in a direction orthogonal to the first direction, and the first channel and the second channel can be laterally offset such that the second channel does not cross over the first channel. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US11934764B2

公开(公告)日：2024-03-19

申请号：US17362662

申请日：2021-06-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Richard Schultz ,  Wenyi Yin ,  Tanmoy Saha

IPC: G06F30/398 ,  G06F30/392 ,  H01L27/02

CPC classification number: G06F30/398 ,  G06F30/392 ,  H01L27/0207

Abstract: Manufacturing a semiconductor chip based on redefining tolerance rules to create an otherwise prohibited structure including redefining a tolerance rule to permit creation of a minimum area metal trench structure violating the tolerance rule during a routing operation; and fabricating the minimum area metal trench structure on the semiconductor substrate based on the redefined tolerance rule.

公开(公告)号：US11742289B2

公开(公告)日：2023-08-29

申请号：US17317510

申请日：2021-05-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Richard Schultz

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L21/76816 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53295 ,  H01L21/76843

Abstract: Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.

公开(公告)号：US20200328155A1

公开(公告)日：2020-10-15

申请号：US16382774

申请日：2019-04-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Richard Schultz

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.