公开(公告)号：US10985085B2

公开(公告)日：2021-04-20

申请号：US16413467

申请日：2019-05-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian Hu ,  Chih-Pin Hung ,  Meng-Kai Shih

IPC: H01L23/427 ,  H01L25/065 ,  H01L23/367 ,  F28D15/04

Abstract: A thermal conductive device includes a first conductive plate, a second conductive plate, a plurality of wicks and a fluid. The first conductive plate has a first portion adjacent to edges of the first conductive plate and a second portion far away from the edges. The second conductive plate has a first portion adjacent to edges of the first conductive plate and a second portion far away from the edges. The first portion and the second portion of the first conductive plate are respectively connected to the first portion and the second portion of the second conductive plate to define a chamber. The plurality of wicks are disposed within the chamber. The fluid is disposed within the chamber.

公开(公告)号：US10658257B1

公开(公告)日：2020-05-19

申请号：US16178241

申请日：2018-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long Chen ,  Chih-Pin Hung ,  Ming-Hung Chen

IPC: H01L23/29 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package structure includes a semiconductor die, at least one wiring structure, an encapsulant and a plurality of conductive elements. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The encapsulant surrounds the semiconductor die. The encapsulant is formed from an encapsulating material, and a Young's Modulus of the encapsulant is from 0.001 GPa to 1 GPa. The conductive elements are embedded in the encapsulant, and are electrically connected to the at least one wiring structure.

公开(公告)号：US11837566B2

公开(公告)日：2023-12-05

申请号：US17534358

申请日：2021-11-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mei-Ju Lu ,  Chi-Han Chen ,  Chang-Yu Lin ,  Jr-Wei Lin ,  Chih-Pin Hung

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17177 ,  H01L2224/73204 ,  H01L2224/81951

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

公开(公告)号：US11777191B2

公开(公告)日：2023-10-03

申请号：US17133369

申请日：2020-12-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yu Ho ,  Sheng-Chi Hsieh ,  Chih-Pin Hung

IPC: H01Q1/22 ,  H01L23/66 ,  H01Q1/52 ,  H01Q25/00

CPC classification number: H01Q1/2283 ,  H01L23/66 ,  H01Q1/523 ,  H01Q25/005 ,  H01L2223/6677

Abstract: The present disclosure relates to a wireless communication module. The wireless communication module includes a first antenna layer and a second antenna layer non-coplanar with the second antenna layer. An electromagnetic wave of the first antenna and the second antenna are configured to have far-field interference to each other.

公开(公告)号：US11227823B2

公开(公告)日：2022-01-18

申请号：US16853396

申请日：2020-04-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan Chen ,  Chih-Pin Hung

IPC: H05K1/11 ,  H05K1/14 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H05K1/02

Abstract: A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.

公开(公告)号：US11183474B2

公开(公告)日：2021-11-23

申请号：US16673699

申请日：2019-11-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mei-Ju Lu ,  Chi-Han Chen ,  Chang-Yu Lin ,  Jr-Wei Lin ,  Chih-Pin Hung

IPC: H01L23/00

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

公开(公告)号：US10886263B2

公开(公告)日：2021-01-05

申请号：US15721257

申请日：2017-09-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： William T. Chen ,  John Richard Hunt ,  Chih-Pin Hung ,  Chen-Chao Wang ,  Chih-Yi Huang

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H01L23/13 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/04 ,  H01L25/065

Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

公开(公告)号：US10658319B2

公开(公告)日：2020-05-19

申请号：US16247437

申请日：2019-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin Hung ,  Dao-Long Chen ,  Ying-Ta Chiu ,  Ping-Feng Yang

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US10541198B2

公开(公告)日：2020-01-21

申请号：US15884197

申请日：2018-01-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chin-Li Kao ,  Chang Chi Lee ,  Chih-Pin Hung

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L21/683 ,  H01L21/48 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.

公开(公告)号：US10522508B2

公开(公告)日：2019-12-31

申请号：US15968562

申请日：2018-05-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian Hu ,  Ming-Han Wang ,  Tsun-Lung Hsieh ,  Chih-Yi Huang ,  Chih-Pin Hung

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.