Tertiary winding for coupled inductor structures

    公开(公告)号:US10601330B1

    公开(公告)日:2020-03-24

    申请号:US15697283

    申请日:2017-09-06

    Applicant: Apple Inc.

    Abstract: An embodiment of a system is disclosed, including an inductor, a voltage regulating circuit, a load, and a current detecting circuit. The inductor includes a first wire, a second wire, and a third wire. The third wire is between, and may be inductively coupled to, the first wire and the second wire. The voltage regulating circuit is coupled to a first end of the first wire and a first end of the second wire. The voltage regulating circuit is configured to generate a first current through the first wire and a second current through the second wire. The load is coupled to a second end of the first wire and a second end of the second wire. The current detecting circuit, coupled to ends of the third wire, is configured to generate an output signal based on a third current through the third wire.

    Systems and Methods for Coherent Power Management

    公开(公告)号:US20180232034A1

    公开(公告)日:2018-08-16

    申请号:US15430699

    申请日:2017-02-13

    Applicant: Apple Inc.

    Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

    Power Management Architecture
    8.
    发明申请

    公开(公告)号:US20170220100A1

    公开(公告)日:2017-08-03

    申请号:US15168472

    申请日:2016-05-31

    Applicant: Apple Inc.

    Abstract: In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

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