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1.
公开(公告)号:US11967528B2
公开(公告)日:2024-04-23
申请号:US18307554
申请日:2023-04-26
Applicant: Apple Inc.
Inventor: Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
CPC classification number: H01L21/77 , H01L22/20 , H01L24/32 , H01L24/73 , H01L25/03 , H01L25/16 , H01L25/18 , H01L24/17 , H01L2224/12105 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/17181 , H01L2224/24195 , H01L2924/12 , H01L2924/1205 , H01L2924/1206 , H01L2924/1427 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104
Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
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2.
公开(公告)号:US20210043511A1
公开(公告)日:2021-02-11
申请号:US17080609
申请日:2020-10-26
Applicant: Apple Inc.
Inventor: Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
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公开(公告)号:US20190221365A1
公开(公告)日:2019-07-18
申请号:US16335075
申请日:2017-08-24
Applicant: Apple Inc.
Inventor: David P. Cappabianca , Joseph T. DiBene, II , Shawn Searles , Le Wang , Yizhang Yang , Sean Cian O'Mathuna , Santosh Kulkarni , Paul McCloskey , Zoran Pavlovic , William Lawton , Graeme Maxwell , Joseph O'Brien , Hugh Charles Smiddy
CPC classification number: H01F41/34 , H01F17/0006 , H01F19/00 , H01F2017/008 , H01L28/10
Abstract: An inductor is disclosed, including a first wire, a non-conductive material, and a shell. The non-conductive material may cover the first wire, with a portion of each end of the first wire uncovered. The shell may include a top portion and a bottom portion and include at least one magnetized layer and at least one gap between the first portion and the second portion. The shell may also surround a portion of the non-conductive material.
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4.
公开(公告)号:US09935076B1
公开(公告)日:2018-04-03
申请号:US15264087
申请日:2016-09-13
Applicant: Apple Inc.
Inventor: Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
CPC classification number: H01L21/77 , H01L24/17 , H01L25/03 , H01L25/16 , H01L25/18 , H01L2224/12105 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/17181 , H01L2224/24195 , H01L2924/1427 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104
Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
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公开(公告)号:US20220406522A1
公开(公告)日:2022-12-22
申请号:US17823017
申请日:2022-08-29
Applicant: Apple Inc.
Inventor: David P. Cappabianca , Joseph T. DiBene, II , Shawn Searles , Le Wang , Yizhang Yang , Sean Cian O'Mathuna , Santosh Kulkarni , Paul McCloskey , Zoran Pavlovic , William Lawton , Graeme Maxwell , Joseph O'Brien , Hugh Charles Smiddy
Abstract: An inductor is disclosed, including a first wire, a non-conductive material, and a shell. The non-conductive material may cover the first wire, with a portion of each end of the first wire uncovered. The shell may include a top portion and a bottom portion and include at least one magnetized layer and at least one gap between the first portion and the second portion. The shell may also surround a portion of the non-conductive material.
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公开(公告)号:US10601330B1
公开(公告)日:2020-03-24
申请号:US15697283
申请日:2017-09-06
Applicant: Apple Inc.
Inventor: David P. Cappabianca , Joseph T. DiBene, II , Shawn Searles
Abstract: An embodiment of a system is disclosed, including an inductor, a voltage regulating circuit, a load, and a current detecting circuit. The inductor includes a first wire, a second wire, and a third wire. The third wire is between, and may be inductively coupled to, the first wire and the second wire. The voltage regulating circuit is coupled to a first end of the first wire and a first end of the second wire. The voltage regulating circuit is configured to generate a first current through the first wire and a second current through the second wire. The load is coupled to a second end of the first wire and a second end of the second wire. The current detecting circuit, coupled to ends of the third wire, is configured to generate an output signal based on a third current through the third wire.
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公开(公告)号:US20180232034A1
公开(公告)日:2018-08-16
申请号:US15430699
申请日:2017-02-13
Applicant: Apple Inc.
Inventor: Joseph T. DiBene, II , Inder M. Sodhi , Keith Cox , Gerard R. Williams, III
IPC: G06F1/32
Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.
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公开(公告)号:US20170220100A1
公开(公告)日:2017-08-03
申请号:US15168472
申请日:2016-05-31
Applicant: Apple Inc.
Inventor: Joseph T. DiBene, II , David A. Hartley , Inder M. Sodhi
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/3237 , G06F1/324 , G06F9/3869 , Y02D10/128 , Y02D10/172
Abstract: In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.
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公开(公告)号:US11430606B2
公开(公告)日:2022-08-30
申请号:US16335075
申请日:2017-08-24
Applicant: Apple Inc.
Inventor: David P. Cappabianca , Joseph T. DiBene, II , Shawn Searles , Le Wang , Yizhang Yang , Sean Cian O'Mathuna , Santosh Kulkarni , Paul McCloskey , Zoran Pavlovic , William Lawton , Graeme Maxwell , Joseph O'Brien , Hugh Charles Smiddy
Abstract: An inductor is disclosed, including a first wire, a non-conductive material, and a shell. The non-conductive material may cover the first wire, with a portion of each end of the first wire uncovered. The shell may include a top portion and a bottom portion and include at least one magnetized layer and at least one gap between the first portion and the second portion. The shell may also surround a portion of the non-conductive material.
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公开(公告)号:US10281965B2
公开(公告)日:2019-05-07
申请号:US15430686
申请日:2017-02-13
Applicant: Apple Inc.
Inventor: Joseph T. DiBene, II , Inder M. Sodhi , Gerard R. Williams, III
IPC: G06F1/26 , G06F1/32 , G06F1/3287 , G06F1/3296 , G06F1/324
Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.
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