公开(公告)号：US20140258761A1

公开(公告)日：2014-09-11

申请号：US14283452

申请日：2014-05-21

Applicant: Apple Inc.

Inventor： Nicholas C. Seroff

IPC: G06F1/32

CPC classification number: G06F1/3268 ,  G06F1/26 ,  G06F1/3206

Abstract: Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget.

Abstract translation: 公开了用于异步管理访问请求以控制功率消耗的系统和方法。 在某些情况下，通过异步管理系统内的电源，NVM的多个管芯可以同时抽出电流以匹配电力需求。 特别地，系统的仲裁器可以接收多个请求来绘制电流，其中每个请求可以与NVM的不同裸片相关联。 在一些实施例中，仲裁器可以使用请求的到达时间来确定服务顺序（例如，先入先出的方案）。 在其他实施例中，只要对多个请求的服务不超过功率预算，仲裁器可以同时服务多个请求。

公开(公告)号：US09164680B2

公开(公告)日：2015-10-20

申请号：US14147700

申请日：2014-01-06

Applicant: Apple Inc.

Inventor： Nicholas C. Seroff ,  Anthony Fai ,  Nir Jacob Wakrat

IPC: G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F3/0611 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0635 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/1684 ,  G06F2212/7204 ,  Y02D10/154

Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

Abstract translation: 提供了用于在非易失性存储器（“NVM”）系统中改善通信的系统和方法。 系统可以在多个通信通道之间切换，以提供主机设备与系统中包含的NVM管芯之间的点对点通信。 主机设备可以在扩展到系统的一个或多个存储器控制器的多个通信通道之间切换，并且存储器控制器可以在延伸到NVM管芯的多个通信通道之间切换。 功率岛可以并入到系统中以电隔离与非活动通信信道相关联的系统组件。

公开(公告)号：US08874942B2

公开(公告)日：2014-10-28

申请号：US14283452

申请日：2014-05-21

Applicant: Apple Inc.

Inventor： Nicholas C. Seroff

IPC: G06F1/00 ,  G06F1/26 ,  G06F11/30 ,  G06F1/32

CPC classification number: G06F1/3268 ,  G06F1/26 ,  G06F1/3206

Abstract: Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget.

公开(公告)号：US20140112079A1

公开(公告)日：2014-04-24

申请号：US14144041

申请日：2013-12-30

Applicant: Apple Inc.

Inventor： Nir J. Wakrat ,  Daniel J. Post ,  Kenneth L. Herman ,  Vadim Khmelnitsky ,  Nicholas C. Seroff ,  Hsiao H. Thio ,  Matthew J. Byom

IPC: G11C16/30

CPC classification number: G11C16/30 ,  G06F1/26 ,  G06F1/3203

Abstract: Systems and methods are disclosed for managing the peak power consumption of a system, such as a non-volatile memory system (e.g., flash memory system). The system can include multiple subsystems and a controller for controlling the subsystems. Each subsystem may have a current profile that is peaky. Thus, the controller may control the peak power of the system by, for example, limiting the number of subsystems that can perform power-intensive operations at the same time or by aiding a subsystem in determining the peak power that the subsystem may consume at any given time.

Abstract translation: 公开了用于管理诸如非易失性存储器系统（例如，闪存系统）的系统的峰值功率消耗的系统和方法。 该系统可以包括多个子系统和用于控制子系统的控制器。 每个子系统可以具有峰值的当前轮廓。 因此，控制器可以通过例如限制可以同时执行功率密集型操作的子系统的数量来控制系统的峰值功率，或通过辅助子系统来确定子系统可能消耗的峰值功率 给定时间

公开(公告)号：US09472243B2

公开(公告)日：2016-10-18

申请号：US14330774

申请日：2014-07-14

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Nicholas C. Seroff

IPC: G11C5/06 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/552 ,  H01L25/16 ,  H01L29/06

CPC classification number: G11C5/06 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/17 ,  H01L24/24 ,  H01L24/25 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/2541 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/49175 ,  H01L2225/06537 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/30107 ,  H01L2924/00

Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Abstract translation: 为叠层半导体存储器件提供系统和方法。 层叠的半导体存储器件可以包括非易失性存储器控制器，以堆叠构造布置的多个非易失性存储器管芯和封装衬底。 存储器控制器和存储器管芯可以通过延伸穿过封装衬底的通孔彼此耦合。 可以使用垂直互连处理来将非易失性存储器管芯彼此以及其它系统部件电连接。 存储器控制器可以倒装芯片接合到外部电路，例如另一个半导体器件或印刷电路板。

公开(公告)号：US20140321189A1

公开(公告)日：2014-10-30

申请号：US14330774

申请日：2014-07-14

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Nicholas C. Seroff

IPC: G11C5/06 ,  H01L23/552 ,  H01L23/522 ,  H01L23/00

CPC classification number: G11C5/06 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/17 ,  H01L24/24 ,  H01L24/25 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/2541 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/49175 ,  H01L2225/06537 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/30107 ,  H01L2924/00

Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Abstract translation: 为叠层半导体存储器件提供系统和方法。 堆叠的半导体存储器件可以包括非易失性存储器控制器，以堆叠配置布置的多个非易失性存储器管芯和封装衬底。 存储器控制器和存储器管芯可以通过延伸穿过封装衬底的通孔彼此耦合。 可以使用垂直互连处理来将非易失性存储器管芯彼此以及其它系统部件电连接。 存储器控制器可以倒装芯片接合到外部电路，例如另一个半导体器件或印刷电路板。

公开(公告)号：US20140164717A1

公开(公告)日：2014-06-12

申请号：US14147700

申请日：2014-01-06

Applicant: Apple Inc.

Inventor： Nicholas C. Seroff ,  Anthony Fai ,  Nir Jacob Wakrat

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0635 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/1684 ,  G06F2212/7204 ,  Y02D10/154

Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

Abstract translation: 提供了用于在非易失性存储器（“NVM”）系统中改善通信的系统和方法。 系统可以在多个通信通道之间切换，以提供主机设备与系统中包含的NVM管芯之间的点对点通信。 主机设备可以在扩展到系统的一个或多个存储器控制器的多个通信通道之间切换，并且存储器控制器可以在延伸到NVM管芯的多个通信通道之间切换。 功率岛可以并入到系统中以电隔离与非活动通信信道相关联的系统组件。