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    Decoding status flag techniques for memory circuits
    1.
    发明授权
    Decoding status flag techniques for memory circuits 有权

    公开(公告)号：US12248369B2

    公开(公告)日：2025-03-11

    申请号：US18323178

    申请日：2023-05-24

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

    IPC: G06F11/10 ,  G06F11/07

    Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.

    Data Corruption Tracking for Memory Reliability
    2.
    发明公开
    Data Corruption Tracking for Memory Reliability 审中-公开

    公开(公告)号：US20230251930A1

    公开(公告)日：2023-08-10

    申请号：US17804932

    申请日：2022-06-01

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

    IPC: G06F11/10 ,  G06F11/07

    CPC classification number: G06F11/1064 ,  G06F11/106 ,  G06F11/076 ,  G06F11/0772

    Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.

    Scalable Cache Coherency Protocol
    3.
    发明申请
    Scalable Cache Coherency Protocol 有权

    公开(公告)号：US20220083472A1

    公开(公告)日：2022-03-17

    申请号：US17315725

    申请日：2021-05-10

    Applicant: Apple Inc.

    Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund

    IPC: G06F12/0815

    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

    Decoding Status Flag Techniques for Memory Circuits
    6.
    发明公开
    Decoding Status Flag Techniques for Memory Circuits 审中-公开

    公开(公告)号：US20230325274A1

    公开(公告)日：2023-10-12

    申请号：US18323178

    申请日：2023-05-24

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

    IPC: G06F11/07 ,  G06F11/10

    CPC classification number: G06F11/1064 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/106

    Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.

    Memory error tracking and logging
    9.
    发明授权
    Memory error tracking and logging 有权

    公开(公告)号：US12253913B2

    公开(公告)日：2025-03-18

    申请号：US18438802

    申请日：2024-02-12

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Derek R. Kumar ,  Bernard J. Semeria ,  James Vash ,  Era K. Nangia ,  Gregory S. Mathews

    IPC: G06F11/10 ,  G06F11/07

    Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

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