公开(公告)号：US20240021571A1

公开(公告)日：2024-01-18

申请号：US17867027

申请日：2022-07-18

Applicant: Applied Materials, Inc.

Inventor： Anup PANCHOLI ,  Marvin Louis BERNT ,  Ronald Patrick HUEMOELLER ,  Avinash SHANTARAM ,  Vincent DICAPRIO

IPC: H01L23/00 ,  H01L21/48

CPC classification number: H01L24/80 ,  H01L21/486 ,  H01L24/08 ,  H01L25/0652

Abstract: Methods for bonding semiconductor surfaces leverage hybrid bonding processes to enable heterogeneous integration architectures. In some embodiments, the methods may comprise forming a semiconductor structure on a silicon-based substrate with a first set of exposed conductive connections on a top surface of the semiconductor structure. The first set of exposed conductive connections having a pitch of less than approximately 10 microns. Forming an advanced rectangular substrate panel with a second set of exposed conductive connections. The second set of exposed conductive connections having a pitch of less than approximately 10 microns. Bonding a top surface of the semiconductor structure to a top surface of the advanced rectangular substrate panel using a hybrid bonding process to bond the semiconductor structure to the advanced rectangular substrate panel.

公开(公告)号：US20230187370A1

公开(公告)日：2023-06-15

申请号：US18075141

申请日：2022-12-05

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Giorgio CELLERE ,  Diego TONINI ,  Vincent DICAPRIO ,  Kyuil CHO

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/10 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H05K1/02 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/105 ,  H01L23/66 ,  H01Q1/2283 ,  H01Q1/243 ,  H05K1/0243 ,  H01L21/50 ,  H01L21/76802 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2021/60007

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

公开(公告)号：US20240170452A1

公开(公告)日：2024-05-23

申请号：US17992167

申请日：2022-11-22

Applicant: Applied Materials, Inc.

Inventor： Anup PANCHOLI ,  Marvin Louis BERNT ,  Vincent DICAPRIO ,  Ronald Patrick HUEMOELLER

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L24/97 ,  H01L21/304 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/80 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/97

Abstract: Methods for substrate processing include attaching a plurality of dies to a first carrier, wherein each die has a first side and a second side opposite the first side, wherein the first side is attached to the first carrier and wherein the plurality of dies are spaced horizontally from one another on the first carrier; filling spaces between the plurality of dies and covering the second sides of the plurality of dies with a dielectric or metal; grinding or polishing the dielectric or metal covering the second sides and grinding or polishing the second sides until the second sides are exposed and the plurality of dies have a substantially uniform thickness; and after grinding or polishing, dishing die faces of the plurality of dies to a desired dishing profile.

公开(公告)号：US20220262652A1

公开(公告)日：2022-08-18

申请号：US17177882

申请日：2021-02-17

Applicant: Applied Materials, Inc.

Inventor： Randy A. HARRIS ,  Coby Scott GROVE ,  Paul Zachary WIRTH ,  Avinash SHANTARAM ,  Alpay YILMAZ ,  Amir NISSAN ,  Vincent DICAPRIO

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/687

Abstract: Methods and apparatus bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing a substrate includes: an equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates; and a plurality of automation modules coupled to each other and having a first automation module coupled to the EFEM, wherein each of the plurality of automation modules include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer configured to hold a plurality of the one or more types of substrates, and wherein the transfer chamber includes a transfer robot configured to transfer the one or more types of substrates between the buffer, the one or more process chambers, and a buffer disposed in an adjacent automation module of the plurality of automation modules.

公开(公告)号：US20240194503A1

公开(公告)日：2024-06-13

申请号：US18586209

申请日：2024-02-23

Applicant: Applied Materials, Inc.

Inventor： Randy A. HARRIS ,  Coby Scott GROVE ,  Paul Zachary WIRTH ,  Avinash SHANTARAM ,  Alpay YILMAZ ,  Amir NISSAN ,  Jitendra Ratilal BHIMJIYANI ,  Niranjan PINGLE ,  Vincent DICAPRIO

IPC: H01L21/67 ,  H01L21/687 ,  H01L23/00

CPC classification number: H01L21/6719 ,  H01L21/67121 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67294 ,  H01L21/68707 ,  H01L24/97

Abstract: Methods and apparatus for bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing substrates includes: an equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates; and a plurality of automation modules coupled to each other and having a first automation module coupled to the EFEM, wherein each of the plurality of automation modules include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer, and wherein the transfer chamber includes a transfer robot configured to transfer the one or more types of substrates, wherein at least one of the plurality of automation modules include a bonder chamber and at least one of the plurality of automation modules include a wet clean chamber.

公开(公告)号：US20220171281A1

公开(公告)日：2022-06-02

申请号：US17673951

申请日：2022-02-17

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Han-Wen CHEN ,  Chintan BUCH ,  Steven VERHAVERBEKE ,  Vincent DICAPRIO

IPC: G03F7/00 ,  H01L21/768 ,  G03F7/20

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 μm.

公开(公告)号：US20210159160A1

公开(公告)日：2021-05-27

申请号：US16886704

申请日：2020-05-28

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Kurtis LESCHKIES ,  Roman GOUK ,  Chintan BUCH ,  Vincent DICAPRIO ,  Bernhard STONAS ,  Jean DELMAS

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US20200243432A1

公开(公告)日：2020-07-30

申请号：US16256809

申请日：2019-01-24

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Kyuil CHO ,  Prayudi LIANTO ,  Guan Huei SEE ,  Vincent DICAPRIO

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: A method for producing an electrical component is disclosed using a molybdenum adhesion layer, connecting a polyimide substrate to a copper seed layer and copper plated attachment.

公开(公告)号：US20200159113A1

公开(公告)日：2020-05-21

申请号：US16192546

申请日：2018-11-15

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Han-Wen CHEN ,  Chintan BUCH ,  Steven VERHAVERBEKE ,  Vincent DICAPRIO

IPC: G03F7/00 ,  G03F7/20 ,  H01L21/768

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 μm.

公开(公告)号：US20240021533A1

公开(公告)日：2024-01-18

申请号：US18362433

申请日：2023-07-31

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Guan Huei SEE ,  Giback PARK ,  Giorgio CELLERE ,  Diego TONINI ,  Vincent DICAPRIO ,  Kyuil CHO

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/10 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H05K1/02 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/105 ,  H01L23/66 ,  H01Q1/2283 ,  H01Q1/243 ,  H05K1/0243 ,  H01L21/50 ,  H01L21/76802 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2021/60007

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.