公开(公告)号：US20240021571A1

公开(公告)日：2024-01-18

申请号：US17867027

申请日：2022-07-18

Applicant: Applied Materials, Inc.

Inventor： Anup PANCHOLI ,  Marvin Louis BERNT ,  Ronald Patrick HUEMOELLER ,  Avinash SHANTARAM ,  Vincent DICAPRIO

IPC: H01L23/00 ,  H01L21/48

CPC classification number: H01L24/80 ,  H01L21/486 ,  H01L24/08 ,  H01L25/0652

Abstract: Methods for bonding semiconductor surfaces leverage hybrid bonding processes to enable heterogeneous integration architectures. In some embodiments, the methods may comprise forming a semiconductor structure on a silicon-based substrate with a first set of exposed conductive connections on a top surface of the semiconductor structure. The first set of exposed conductive connections having a pitch of less than approximately 10 microns. Forming an advanced rectangular substrate panel with a second set of exposed conductive connections. The second set of exposed conductive connections having a pitch of less than approximately 10 microns. Bonding a top surface of the semiconductor structure to a top surface of the advanced rectangular substrate panel using a hybrid bonding process to bond the semiconductor structure to the advanced rectangular substrate panel.

公开(公告)号：US20180005881A1

公开(公告)日：2018-01-04

申请号：US15200836

申请日：2016-07-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi LIANTO ,  Sam LEE ,  Charles SHARBONO ,  Marvin Louis BERNT ,  Guan Huei SEE ,  Arvind SUNDARRAJAN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76804 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329

Abstract: A method of processing a semiconductor substrate includes: immersing a substrate in a first bath, wherein the substrate comprises a barrier layer, a conductive seed layer, and a patterned photoresist layer defining an opening; providing a first electric current between the conductive seed layer and a first anode disposed in electrical contact with the first bath to deposit a conductive material within the opening; stripping the patterned photoresist layer; immersing the substrate in a second bath; providing a second electric current that is a reverse of the first electric current between the conductive seed layer plus the conductive material and a second anode disposed in electrical contact with the second bath; etching the conductive seed layer from atop a field region of the barrier layer; and etching the barrier layer from atop a field region of the substrate.

公开(公告)号：US20240170452A1

公开(公告)日：2024-05-23

申请号：US17992167

申请日：2022-11-22

Applicant: Applied Materials, Inc.

Inventor： Anup PANCHOLI ,  Marvin Louis BERNT ,  Vincent DICAPRIO ,  Ronald Patrick HUEMOELLER

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L24/97 ,  H01L21/304 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/80 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/97

Abstract: Methods for substrate processing include attaching a plurality of dies to a first carrier, wherein each die has a first side and a second side opposite the first side, wherein the first side is attached to the first carrier and wherein the plurality of dies are spaced horizontally from one another on the first carrier; filling spaces between the plurality of dies and covering the second sides of the plurality of dies with a dielectric or metal; grinding or polishing the dielectric or metal covering the second sides and grinding or polishing the second sides until the second sides are exposed and the plurality of dies have a substantially uniform thickness; and after grinding or polishing, dishing die faces of the plurality of dies to a desired dishing profile.

公开(公告)号：US20250038137A1

公开(公告)日：2025-01-30

申请号：US18225286

申请日：2023-07-24

Applicant: Applied Materials, Inc.

Inventor： Prayudi LIANTO ,  Marvin Louis BERNT ,  Tapash CHAKRABORTY ,  Yin Wei LIM ,  Jing XU

IPC: H01L23/00

Abstract: A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. In some embodiments, the deposited copper material in the structure has a grain orientation normal to a horizontal surface of the structure.

公开(公告)号：US20230307320A1

公开(公告)日：2023-09-28

申请号：US17705239

申请日：2022-03-25

Applicant: Applied Materials, Inc.

Inventor： Marvin Louis BERNT ,  Jon WOODYARD

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L23/53238 ,  H01L21/76898 ,  H01L21/76877

Abstract: Methods and apparatus for single side filling of through-vias in a substrate are provided herein. In some embodiments, a method of filling through-vias in a substrate includes: coupling a first side of the substrate having through-vias to a carrier plate with an adhesive layer; exposing the through-vias to a conductive layer disposed between the carrier plate and the first side of the substrate; and plating the substrate using the conductive layer as a conductive seed layer to fill the through-vias with a conductive material.

公开(公告)号：US20240069448A1

公开(公告)日：2024-02-29

申请号：US17900124

申请日：2022-08-31

Applicant: Applied Materials, Inc.

Inventor： Prayudi LIANTO ,  Liu JIANG ,  Marvin Louis BERNT ,  El Mehdi BAZIZI ,  Guan Huei SEE

IPC: G03F7/20 ,  G03F9/00

CPC classification number: G03F7/70633 ,  G03F9/7088

Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

公开(公告)号：US20230304183A1

公开(公告)日：2023-09-28

申请号：US18118336

申请日：2023-03-07

Applicant: Applied Materials, Inc.

Inventor： Marvin Louis BERNT ,  Jon WOODYARD ,  Niranjan KHASGIWALE ,  Vincent DICAPRIO

IPC: C25D5/02 ,  H01L21/288 ,  H01L21/66 ,  C25D21/12 ,  G03F1/70

CPC classification number: C25D5/022 ,  H01L21/2885 ,  H01L22/12 ,  C25D21/12 ,  G03F1/70

Abstract: Methods and apparatus for electroplating a substrate incorporate aspects of digital lithography and feedback from electroplating processes to improve characteristics of plating material based on die patterns. In some embodiments, a method of electroplating a substrate may include receiving a die design, forming a first lithographic pattern for a first substrate based on the die design, using a digital lithography process to pattern the first substrate with the first lithographic pattern, using an electroplating process to deposit material on the first substrate, using a metrology process to determine at least one parameter of the deposited material on the first substrate, and forming a second lithographic pattern from the first lithographic pattern for a second substrate based, at least in part, on the at least one parameter received directly from the metrology process on the first substrate by the digital lithographic process for the second substrate.

公开(公告)号：US20230086742A1

公开(公告)日：2023-03-23

申请号：US17482562

申请日：2021-09-23

Applicant: Applied Materials, Inc.

Inventor： Marvin Louis BERNT

IPC: H01L21/288 ,  H01L21/768 ,  H01L23/532

Abstract: A method of depositing a metal material on an isolated seed layer uses a barrier layer as a conductive path for plating. The method may include depositing a barrier layer on a substrate wherein the barrier layer provides adhesion for seed layer material and inhibits migration of the seed layer material, forming at least one isolated seed layer area on the barrier layer on the substrate, and depositing the metal material on the at least one isolated seed layer area using an electrochemical deposition process wherein the barrier layer provides a current path to deposit the metal material on the at least one isolated seed layer area.