公开(公告)号：US20040023502A1

公开(公告)日：2004-02-05

申请号：US10211453

申请日：2002-08-02

Applicant: APPLIED MATERIALS INC.

Inventor： Eugene Tzou ,  Jie Yuan ,  Yan Ye

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/02115 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/3146 ,  H01L21/32139

Abstract: A method for etching a metal layer formed on a substrate to form a metal line, using an amorphous carbon layer as a pattern mask. One embodiment of the method of the invention etches a metal layer formed on a substrate, for forming a metal line, by depositing an amorphous carbon layer on the metal layer, patterning the amorphous carbon layer to provide a pattern mask on the metal layer, thus exposing portions of said metal layer; and etching the exposed portions of the metal layer, to form a metal line. In an embodiment, the metal layer comprises a copper layer.

Abstract translation: 一种使用无定形碳层作为图案掩模蚀刻形成在基板上以形成金属线的金属层的方法。 本发明方法的一个实施方案是通过在金属层上沉积无定形碳层来蚀刻形成在基底上的金属层，以形成金属线，图案化无定形碳层以在金属层上提供图案掩模，从而 暴露所述金属层的部分; 并蚀刻金属层的暴露部分，形成金属线。 在一个实施例中，金属层包括铜层。

公开(公告)号：US20030111961A1

公开(公告)日：2003-06-19

申请号：US10027732

申请日：2001-12-19

Applicant: Applied Materials, Inc.

Inventor： Dan Katz ,  Douglas A. Buchberger JR. ,  Yan Ye ,  Robert B. Hagen ,  Xiaoye Zhao ,  Ananda H. Kumar ,  Kang-Lie Chiang ,  Hamid Noorbakhsh ,  Shiang-Bau Wang

IPC: H01J007/24

CPC classification number: H01J37/3244

Abstract: The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate, the back and front plates bonded together and forming an assembly. The assembly includes an array of holes through the front plate and communicating with the chamber, at least one gas flow-controlling orifice through the back plate and communicating between the manifold and at least one of the holes, the orifice having a diameter that determines gas flow rate to the at least one hole. In addition, an array of pucks is at least generally congruent with the array of holes and disposed within respective ones of the holes to define annular gas passages for gas flow through the front plate into the chamber, each of the annular gas passages being non-aligned with the orifice.

Abstract translation: 本发明体现在用于处理半导体晶片的等离子体反应器中，该反应器具有气体分配板，该气体分配板包括在该腔室中的前板和在前板的外侧上的后板，该气体分配板包括邻近的气体歧管 背板，后板和前板结合在一起并形成组件。 组件包括穿过前板并与腔室连通的孔阵列，至少一个通过后板的气体流量控制孔，并在歧管和至少一个孔之间连通，孔口具有确定气体的直径 至少一个孔的流速。 此外，一组圆盘至少大体上与孔阵列一致，并且设置在孔的相应孔内，以限定用于气体流过前板进入腔室的环形气体通道，每个环形气体通道是非限制性的， 与孔对齐。

公开(公告)号：US20040198062A1

公开(公告)日：2004-10-07

申请号：US10674700

申请日：2003-09-29

Applicant: Applied Materials, Inc.

Inventor： Yan Ye ,  Xiaoye Zhao ,  Hong Du

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/76808 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/7684

Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).

Abstract translation: 公开了一种制造集成电路器件的互连结构（例如双镶嵌互连结构等）的方法。 使用包括成像膜和有机平坦化膜的双层掩模制造互连结构。 当形成互连结构时，双层掩模用于去除接触孔，沟槽和下面的导电线之间的光刻未对准。 此外，牺牲层可以用于在互连结构的随后的平坦化期间保护金属间电介质（IMD）层。 牺牲层可以由非晶硅（Si），氮化钛（TiN），钨（W）等形成。 互连结构可以由金属（例如铜（Cu），铝（Al），钽（Ti），钨（W），钛（Ti）等）或导电化合物（例如，氮化钽 （TaN），氮化钛（TiN），氮化钨（WN）等）。

公开(公告)号：US20030218427A1

公开(公告)日：2003-11-27

申请号：US10192271

申请日：2002-07-09

Applicant: Applied Materials, Inc.

Inventor： Daniel J. Hoffman ,  Matthew L. Miller ,  Jang Gyoo Yang ,  Heeyeop Chae ,  Michael Barnes ,  Tetsuya Ishikawa ,  Yan Ye

IPC: H01J007/24

CPC classification number: H01J37/32091 ,  H01J37/3244 ,  H01J37/32623 ,  H01J37/3266

Abstract: A plasma reactor includes a vacuum enclosure including a side wall and a ceiling defining a vacuum chamber, and a workpiece support within the chamber and facing the ceiling for supporting a planar workpiece, the workpiece support and the ceiling together defining a processing region between the workpiece support and the ceiling. Process gas inlets furnish a process gas into the chamber. A plasma source power electrode is connected to an RF power generator for capacitively coupling plasma source power into the chamber for maintaining a plasma within the chamber. The reactor further includes at least a first overhead solenoidal electromagnet adjacent the ceiling, the overhead solenoidal electromagnet, the ceiling, the sidewall and the workpiece support being located along a common axis of symmetry. A current source is connected to the first solenoidal electromagnet and furnishes a first electric current in the first solenoidal electromagnet whereby to generate within the chamber a magnetic field which is a function of the first electric current, the first electric current having a value such that the magnetic field increases uniformity of plasma ion density radial distribution about the axis of symmetry near a surface of the workpiece support.

Abstract translation: 等离子体反应器包括真空外壳，其包括限定真空室的侧壁和顶板，以及腔室内的工件支撑件，并面向天花板以支撑平面工件，工件支撑件和天花板一起限定了工件之间的加工区域 支持和天花板。 工艺气体入口将工艺气体提供到腔室中。 等离子体源功率电极连接到RF功率发生器，用于将等离子体源功率电容耦合到腔室中，以在腔室内维持等离子体。 所述反应器还包括至少邻近所述天花板的顶部螺线管电磁体，所述架空螺线管电磁体，所述天花板，所述侧壁和所述工件支撑件沿着公共对称轴线定位。 电流源连接到第一螺线管电磁体并且在第一螺线管电磁体中提供第一电流，从而在腔室内产生与第一电流有关的磁场，第一电流具有使得 磁场增加等离子体离子密度在工件支撑表面附近的对称轴的径向分布的均匀性。

公开(公告)号：US20040206309A1

公开(公告)日：2004-10-21

申请号：US10418996

申请日：2003-04-17

Applicant: Applied Materials, Inc.

Inventor： Kallol Bera ,  Yan Ye ,  James D. Carducci ,  Daniel J. Hoffman ,  Steven C. Shannon ,  Douglas A. Buchberger JR.

IPC: C23C016/00

CPC classification number: H01J37/321 ,  H01J37/32633 ,  H01J37/3266

Abstract: An apparatus configured to confine a plasma within a processing region in a plasma processing chamber. In one embodiment, the apparatus includes a ring that has a baffle having a plurality of slots and a plurality of fingers. Each slot is configured to have a width less than the thickness of a plasma sheath contained in the processing region.

Abstract translation: 一种被配置为将等离子体限制在等离子体处理室中的处理区域内的装置。 在一个实施例中，该装置包括具有挡板的环，该挡板具有多个槽和多个指状物。 每个槽被构造成具有小于包含在处理区域中的等离子体护套的厚度的宽度。

公开(公告)号：US20030111181A1

公开(公告)日：2003-06-19

申请号：US10028646

申请日：2001-12-19

Applicant: Applied Materials, Inc.

Inventor： Shiang-Bau Wang ,  Daniel J. Hoffman ,  Chunshi Cui ,  Yan Ye ,  Gerardo Delgadino ,  David McParland ,  Matthew L. Miller ,  Douglas A. Buchberger JR. ,  Steven C. Shannon

IPC: C23F001/00 ,  C23C016/00

CPC classification number: H01J37/321

Abstract: An inductive antenna of a plasma reactor for processing a semiconductor wafer is connected to a radio frequency (RF) power source, and consists of a conductor arranged in successive loops that wind in opposing directions, adjacent pairs of the successive loops having facing portions in which current flow is parallel, the facing portions being sufficiently close to at least nearly share a common current path, whereby to form transitions across the facing portions between opposing magnetic polarizations.

公开(公告)号：US20030109143A1

公开(公告)日：2003-06-12

申请号：US10016562

申请日：2001-12-12

Applicant: Applied Materials, Inc.

Inventor： Chang-Lin Hsieh ,  Jie Yuan ,  Hui Chen ,  Theodoros Panagopoulos ,  Yan Ye

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/31116 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76808 ,  H01L21/76835

Abstract: A method is provided for etching a dielectric structure. The dielectric structure comprises: (a) a layer of undoped silicon oxide or F-doped silicon oxide; and (b) a layer of C,H-doped silicon oxide. The dielectric structure is etched in a plasma-etching step, which plasma-etching step is conducted using a plasma source gas that comprises nitrogen atoms and fluorine atoms. As one example, the plasma source gas can comprise a gaseous species that comprises one or more nitrogen atoms and one or more fluorine atoms (e.g., NF3). As another example, the plasma source gas can comprise (a) a gaseous species that comprises one or more nitrogen atoms (e.g., N2) and (b) a gaseous species that comprises one or more fluorine atoms (e.g., a fluorocarbon gas such as CF4). In this etching step, the layer of C,H-doped silicon oxide is preferentially etched relative to the layer of undoped silicon oxide or F-doped silicon oxide. The method of the present invention is applicable, for example, to dual damascene structures.

Abstract translation: 提供了蚀刻电介质结构的方法。 电介质结构包括：（a）一层未掺杂的氧化硅或掺杂F的氧化硅; 和（b）C，H掺杂的氧化硅层。 在等离子体蚀刻步骤中蚀刻电介质结构，使用包含氮原子和氟原子的等离子体源气体进行等离子体蚀刻步骤。 作为一个示例，等离子体源气体可以包括包含一个或多个氮原子和一个或多个氟原子（例如NF 3）的气态物质。 作为另一示例，等离子体源气体可以包括（a）包含一个或多个氮原子（例如，N 2）的气体物质和（b）包含一个或多个氟原子的气态物质（例如，碳氟化合物气体，例如 CF4）。 在该蚀刻步骤中，相对于未掺杂的氧化硅层或掺杂F的氧化硅层优先蚀刻C，H掺杂的氧化硅层。 本发明的方法例如适用于双镶嵌结构。

公开(公告)号：US20040157453A1

公开(公告)日：2004-08-12

申请号：US10745344

申请日：2003-12-22

Applicant: APPLIED MATERIALS, INC.

Inventor： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/76826 ,  H01L21/76811 ,  H01L21/76813

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract translation: 一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。

公开(公告)号：US20040149699A1

公开(公告)日：2004-08-05

申请号：US10754280

申请日：2004-01-08

Applicant: Applied Materials, Inc.

Inventor： Daniel J. Hofman ,  Jennifer Y. Sun ,  Senh Thach ,  Yan Ye

IPC: B23K010/00

CPC classification number: H01J37/32082 ,  H01J37/32183

Abstract: A gas distribution ceiling electrode for use as a capacitive source power applicator and gas distribution showerhead in a plasma reactor includes a metal base and a process-compatible protective layer on the interior surface of he electrode having a dopant impurity concentration within a range corresponding to a minimal change in RF power absorption in the protective layer at an RF source power frequency with changes in coating temperature and or thickness. The metal base may have a set of first arcuately slotted gas passages and a set of pressure-dropping orifices coinciding axially with the top ends of the gas passages. The protective coating a set of arcuately slotted gas passages in registration gas passages of the metal base. The pressure drop in the orifices and the electric field drop in the slotted gas passages are both sufficient to maintain the pressure and electric field within the gas passages within a range that prevents arcing.

Abstract translation: 用作等离子体反应器中的电容源功率施加器和气体分配喷头的气体分配顶板电极包括在电极内表面上的金属基底和与工艺相容的保护层，其中掺杂剂杂质浓度在对应于 RF源功率频率随着涂层温度和/或厚度的变化而在保护层中RF功率吸收的最小变化。 金属基底可以具有一组第一弧形开槽的气体通道和一组与气体通道的顶端轴向重合的压力下降孔。 保护涂层在金属基座的配准气体通道中形成一组弧形开槽的气体通道。 孔口中的压降和开槽气体通道中的电场下降足以将气体通道内的压力和电场保持在防止电弧的范围内。

公开(公告)号：US20030235993A1

公开(公告)日：2003-12-25

申请号：US10172243

申请日：2002-06-14

Applicant: Applied Materials, Inc.

Inventor： Terry Leung ,  Qiqun Zheng ,  Chang-Lin Hsieh ,  Yan Ye ,  Takehiko Komatsu

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/31116 ,  H01L21/31144

Abstract: The present invention provides a low-k dielectric etching process with high etching selectivities with respect to adjacent layers of other materials, such as an overlying photoresist mask and an underlying barrier/liner layer. The process comprises the step of exposing a portion of the low-k dielectric layer to a plasma of a process gas that includes a fluorocarbon gas, a nitrogen-containing gas, and an inert gas, wherein the volumetric flow ratio of inert:fluorocarbon gas is in the range of 20:1 to 100:1, and the volumetric flow ratio of fluorocarbon:nitrogen-containing gas is selected to provide a low-k dielectric to photoresist etching selectivity ratio greater than about 5:1 and a low-k dielectric etch rate higher than about 4000 null/min.

Abstract translation: 本发明提供了相对于其它材料的相邻层（例如覆盖光致抗蚀剂掩模和下面的阻挡层/衬里层）具有高蚀刻选择性的低k电介质蚀刻工艺。 该方法包括将低k电介质层的一部分暴露于包括碳氟化合物气体，含氮气体和惰性气体的工艺气体的等离子体的步骤，其中惰性：碳氟化合物气体的体积流量比 在20:1至100:1的范围内，选择碳氟化合物：含氮气体的体积流量比以提供低k电介质至光致抗蚀剂蚀刻选择比大于约5:1，低k 介电蚀刻速率高于约4000 / min。