公开(公告)号：US11386937B2

公开(公告)日：2022-07-12

申请号：US16600483

申请日：2019-10-12

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing single port memory with a bitcell array arranged in columns and rows. The method may include coupling a wordline to the single port memory including coupling the wordline to the columns of the bitcell array. The method may include performing multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using the wordline while performing a write operation in another column of the bitcell array using the wordline, or performing a write operation in one column of the bitcell array using the wordline while performing a read operation in another column of the bitcell array using the same wordline.

公开(公告)号：US20210098032A1

公开(公告)日：2021-04-01

申请号：US16584898

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/16 ,  G11C11/418

Abstract: Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.

公开(公告)号：US20190325948A1

公开(公告)日：2019-10-24

申请号：US15960475

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US10049709B2

公开(公告)日：2018-08-14

申请号：US14986215

申请日：2015-12-31

Applicant: ARM Limited

Inventor： Gus Yeung ,  Fakhruddin Ali Bohra ,  George McNeil Lattimore

IPC: G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  G11C11/413

Abstract: Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.

公开(公告)号：US09824749B1

公开(公告)日：2017-11-21

申请号：US15256200

申请日：2016-09-02

Applicant: ARM Limited

Inventor： Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi ,  Abhishek B. Akkur

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/418 ,  G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/409 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/12

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include precharge circuitry for precharging bitlines to a source voltage level. The integrated circuit may include write assist circuitry having a charge storage element for providing a write assist signal to at least one of the bitlines. The integrated circuit may include read assist circuitry having a switching element for providing charge sharing between the bitlines, the precharge circuitry, and the charge storage element of the write assist circuitry.

公开(公告)号：US09721624B2

公开(公告)日：2017-08-01

申请号：US14581229

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Gus Yeung ,  Fakhruddin Ali Bohra ,  Mudit Bhargava ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/12 ,  G11C7/22

Abstract: A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

公开(公告)号：US20160276000A1

公开(公告)日：2016-09-22

申请号：US14659270

申请日：2015-03-16

Applicant: ARM Limited ,  The Regents of the University of Michigan

Inventor： Mahmood Khayatzadeh ,  Massimo Bruno Alioto ,  David Blaauw ,  Dennis Michael Chen Sylvester ,  Fakhruddin Ali Bohra

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/18 ,  G11C8/16 ,  G11C11/419 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/002 ,  G11C2207/005

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Abstract translation: 本文描述的各种实施方式可以涉及并且可以涉及使用拓扑配置的集成电路的电路。 例如，在一个实现中，这种电路可以包括具有多个存储器单元的存储器阵列。 这种电路还可以包括耦合到存储器阵列并被配置为放大从存储器阵列接收的差分电压电平的一个或多个可重新配置的读出放大器器件。 可重构感测放大器装置可以包括多个读出放大器电路，其被配置为布置成多个拓扑结构中的一种，其中拓扑结构包括并行配置和交叉并行配置。 可重构感测放大器装置还可以包括一个或多个开关，其被配置为基于一个或多个控制位将多个读出放大器电路设置成多个拓扑结构。

公开(公告)号：US08963609B2

公开(公告)日：2015-02-24

申请号：US13782120

申请日：2013-03-01

Applicant: ARM Limited

Inventor： Gus Yeung ,  Srinivasan Srinath ,  Fakhruddin Ali Bohra

IPC: H03L5/00

CPC classification number: H03K19/0185

Abstract: An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion. A contention mitigation circuitry reduces a voltage drop across at least one component within the feedback circuitry in situations when the combinatorial circuitry's performance of the combinatorial operation causes the combinatorial circuitry to switch the voltage on the output node, the contention mitigation circuitry thereby assists the combinatorial circuitry in the output node voltage switching.

Abstract translation: 集成电平移位组合电路在第一电压域中接收多个输入信号，并执行组合操作以在第二电压域中产生输出信号。 电路包括组合电路，其包括在相应的第一和第二电压域中操作的第一组合电路部分和第二组合电路部分。 第二组合电路部分具有输出节点，其电压电平标识输出信号的值，并且包括对由第一组合电路部分产生的中间信号施加电平移位功能的反馈电路。 在组合电路的组合操作的性能导致组合电路切换输出节点上的电压的情况下，争用减轻电路减少了反馈电路内的至少一个组件上的电压降，争用缓解电路因此有助于组合电路 在输出节点电压切换。

公开(公告)号：US11742001B2

公开(公告)日：2023-08-29

申请号：US16860764

申请日：2020-04-28

Applicant: Arm Limited

Inventor： Fakhruddin Ali Bohra ,  Lalit Gupta ,  Shri Sagar Dwivedi

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078

Abstract: Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first set of multiplexers that receives column data from the array of memory cells and provides first multiplexed output data. The device may include output interface circuitry coupled to the output circuitry, and the output interface circuitry may have a second set of multiplexers that receives the first multiplexed output data from the output circuitry and selectively provides second multiplexed output data based on a configurable mode of multiplexed operation.

公开(公告)号：US20210110851A1

公开(公告)日：2021-04-15

申请号：US16709687

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Cyrille Nicolas Dray ,  Ashish Bhardwaj ,  Durgesh Kumar Dubey

IPC: G11C7/10 ,  G11C8/08

Abstract: Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.