公开(公告)号：US08617961B1

公开(公告)日：2013-12-31

申请号：US13551659

申请日：2012-07-18

申请人： Balasubramanian S. Haran ,  Sanjay Mehta ,  Theodorus E. Standaert

发明人： Balasubramanian S. Haran ,  Sanjay Mehta ,  Theodorus E. Standaert

IPC分类号： H01L21/76

CPC分类号： H01L21/76283 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66545

摘要： A method for fin field effect transistor (finFET) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finFET device after formation of the gate region, wherein forming the isolation areas for the finFET device comprises performing one of oxidation or removal of a subset of the plurality of fins.

摘要翻译： 鳍状场效应晶体管（finFET）器件形成的方法包括在衬底上形成多个翅片; 在所述多个翅片上形成栅极区域; 以及在形成栅极区域之后形成用于finFET器件的隔离区域，其中形成用于finFET器件的隔离区域包括执行多个鳍片的子集的氧化或去除之一。

公开(公告)号：US20140024198A1

公开(公告)日：2014-01-23

申请号：US13551659

申请日：2012-07-18

申请人： Balasubramanian S. Haran ,  Sanjay Mehta ,  Theodorus E. Standaert

发明人： Balasubramanian S. Haran ,  Sanjay Mehta ,  Theodorus E. Standaert

IPC分类号： H01L21/76

CPC分类号： H01L21/76283 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66545

摘要： A method for fin field effect transistor (finFET) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finFET device after formation of the gate region, wherein forming the isolation areas for the finFET device comprises performing one of oxidation or removal of a subset of the plurality of fins.

摘要翻译： 鳍状场效应晶体管（finFET）器件形成的方法包括在衬底上形成多个翅片; 在所述多个翅片上形成栅极区域; 以及在形成栅极区域之后形成用于finFET器件的隔离区域，其中形成用于finFET器件的隔离区域包括执行多个鳍片的子集的氧化或去除之一。

公开(公告)号：US08932918B2

公开(公告)日：2015-01-13

申请号：US13598080

申请日：2012-08-29

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/338

CPC分类号： H01L29/7851 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/7849

摘要： A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method further includes diffusing dopants from the punchthrough stopper into the fin structures. The method further includes forming source and drain regions adjacent to the gate structure and fin structures.

摘要翻译： 公开了具有自对准穿通塞子的finFET和制造方法。 该方法包括在栅极结构的侧壁和finFET器件的翅片结构上形成间隔物。 该方法还包括在隔片的下方在翅片结构的暴露的侧壁上形成穿通止动件。 该方法还包括将穿透止动器的掺杂剂扩散到鳍结构中。 该方法还包括形成与栅极结构和鳍结构相邻的源区和漏区。

公开(公告)号：US08772874B2

公开(公告)日：2014-07-08

申请号：US13216554

申请日：2011-08-24

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66803 ,  H01L29/785

摘要： At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.

摘要翻译： 作为平面FET或鳍式FET的结构的场效应晶体管（FET）结构的至少一个漏极侧表面在结构上被惰性或电活性掺杂剂的成角度的离子注入损坏，而至少一个 保护晶体管的源极侧表面不被栅极堆叠和栅极间隔物的注入。 半导体材料的外延生长在至少一个结构损坏的漏极侧表面上延迟，而外延生长在至少一个源极侧表面上没有延迟。 凸起的外延源区域具有比凸起的外延漏极区域更大的厚度，从而提供具有比漏极侧外部电阻更小的源极侧外部电阻并且具有比源极重叠电容更少的漏极侧重叠电容的非对称FET。

公开(公告)号：US08581320B1

公开(公告)日：2013-11-12

申请号：US13476567

申请日：2012-05-21

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L27/108

CPC分类号： H01L27/1288 ,  H01L21/823431 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1211 ,  H01L28/90

摘要： Capacitors include a first electrical terminal that has fins formed from doped semiconductor on a top layer of doped semiconductor on a semiconductor-on-insulator substrate; a second electrical terminal that has an undoped material having bottom surface shape that is complementary to the first electrical terminal, such that an interface area between the first electrical terminal and the second electrical terminal is larger than a capacitor footprint; and a dielectric layer separating the first and second electrical terminals.

摘要翻译： 电容器包括在绝缘体上半导体衬底上的掺杂半导体的顶层上具有由掺杂半导体形成的鳍片的第一电端子; 第二电端子，其具有与第一电端子互补的底表面形状的未掺杂材料，使得第一电端子和第二电端子之间的界面面积大于电容器覆盖区; 以及分隔第一和第二电端子的电介质层。

公开(公告)号：US08569152B1

公开(公告)日：2013-10-29

申请号：US13487413

申请日：2012-06-04

申请人： Veeraraghavan S. Basker ,  Huiming Bu ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Nicolas Loubet ,  Shom Ponoth ,  Stefan Schmitz ,  Theodorus E Standaert ,  Tenko Yamashita

发明人： Veeraraghavan S. Basker ,  Huiming Bu ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Nicolas Loubet ,  Shom Ponoth ,  Stefan Schmitz ,  Theodorus E Standaert ,  Tenko Yamashita

IPC分类号： H01L21/20

CPC分类号： H01L29/66795 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681

摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.

摘要翻译： 描述了制造双外延FinFET的方法。 该方法包括将第一外延材料添加到翅片阵列。 该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。 在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。 该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。 还描述了装置和计算机程序产品。

公开(公告)号：US08703553B2

公开(公告)日：2014-04-22

申请号：US13471955

申请日：2012-05-15

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/8234 ,  H01L27/12

CPC分类号： H01L27/1288 ,  H01L21/823431 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1211 ,  H01L28/90

摘要： Methods for capacitor fabrication include doping a capacitor region of a semiconductor layer in a semiconductor-on-insulator substrate; partially etching the semiconductor layer to produce a first terminal layer comprising doped semiconductor fins on a remaining base of doped semiconductor; forming a dielectric layer over the first terminal layer; and forming a second terminal layer over the dielectric layer in a finFET process.

摘要翻译： 用于电容器制造的方法包括在绝缘体上半导体衬底中掺杂半导体层的电容器区域; 部分地蚀刻半导体层以产生在掺杂半导体的剩余基底上包括掺杂半导体鳍片的第一端子层; 在所述第一端子层上形成介电层; 以及在finFET工艺中在所述介电层上形成第二端子层。

公开(公告)号：US20130319613A1

公开(公告)日：2013-12-05

申请号：US13545456

申请日：2012-07-10

申请人： Veeraraghavan S. Basker ,  Huiming Bu ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Nicolas Loubet ,  Shom Ponoth ,  Stefan Schmitz ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Veeraraghavan S. Basker ,  Huiming Bu ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Nicolas Loubet ,  Shom Ponoth ,  Stefan Schmitz ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/308

CPC分类号： H01L29/66795 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681

摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.

摘要翻译： 描述了制造双外延FinFET的方法。 该方法包括将第一外延材料添加到翅片阵列。 该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。 在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。 该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。 还描述了装置和计算机程序产品。

公开(公告)号：US08592290B1

公开(公告)日：2013-11-26

申请号：US13545456

申请日：2012-07-10

申请人： Veeraraghavan S. Basker ,  Huiming Bu ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Nicolas Loubet ,  Shom Ponoth ,  Stefan Schmitz ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Veeraraghavan S. Basker ,  Huiming Bu ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Nicolas Loubet ,  Shom Ponoth ,  Stefan Schmitz ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/20

CPC分类号： H01L29/66795 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681

摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.

摘要翻译： 描述了制造双外延FinFET的方法。 该方法包括将第一外延材料添加到翅片阵列。 该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。 在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。 该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。 还描述了装置和计算机程序产品。

公开(公告)号：US20130175618A1

公开(公告)日：2013-07-11

申请号：US13343805

申请日：2012-01-05

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L27/088 ,  H01L21/20 ,  H01L21/28

CPC分类号： H01L21/845 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/045

摘要： A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.