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1.发明申请METHOD FOR FORMING ACUTE-ANGLE SPACER FOR NON-ORTHOGONAL FINFET AND THE RESULTING STRUCTURE 审中-公开形成用于非正交FINFET和结构结构的急性角度间隔的方法公开(公告)号：US20090001470A1
公开(公告)日：2009-01-01
申请号：US11768257
申请日：2007-06-26
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： In a method of fabricating a semiconductor finFET transistor for an integrated circuit chip comprising 1) the formation of at least one fin body on the surface of a substrate and 2) the formation of a gate on said fin body in a non-orthogonal orientation relative to the body thereby creating acute angle regions at the crossover of the gate on the body, and 3) the formation of a protective material in the acute angle regions so as to prevent damage to the gate during subsequent fabrication steps. The structure of the finFET transistor comprises such a transistor with protective material in the acute angle regions at the crossover of the gate on the body.
摘要翻译： 一种用于制造用于集成电路芯片的半导体finFET晶体管的方法，包括：1）在衬底的表面上形成至少一个翅片体，以及2）在所述翅片体上以非正交取向相对形成栅极 从而在主体上的栅极交叉处产生锐角区域，以及3）在锐角区域中形成保护材料，以防止在随后的制造步骤期间损坏栅极。 finFET晶体管的结构包括在主体上的栅极交叉处的锐角区域中的这种具有保护材料的晶体管。
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公开(公告)号：US07955926B2
公开(公告)日：2011-06-07
申请号：US12055682
申请日：2008-03-26
IPC分类号： H01L21/00
CPC分类号： H01L21/76224 , H01L21/28123 , H01L29/517
摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.
摘要翻译： 在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。
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公开(公告)号：US07900167B2
公开(公告)日：2011-03-01
申请号：US11923131
申请日：2007-10-24
IPC分类号： G06F17/50
CPC分类号： H01L29/7371 , H01L29/0826 , H01L29/161
摘要： Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
摘要翻译： 公开了具有窄的基本上无间隙的SIC基座的改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管）的设计结构，其具有极小的外部基极的重叠。 此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。 因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。
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公开(公告)号：US07682917B2
公开(公告)日：2010-03-23
申请号：US12016326
申请日：2008-01-18
申请人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
发明人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/7847 , H01L21/324 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes.
摘要翻译： 一次性间隔物直接形成在栅极电极和栅极电介质的侧壁上或紧邻栅电极的侧壁上。 一次性间隔件包括清除氧的材料，例如金属，金属氮化物或具有高氧反应性的半导体材料。 一次性栅极间隔件在随后的高温处理例如应力记忆退火期间吸收任何氧气。 将金属沉积在栅电极和源极和漏极区上并与其反应以形成金属半导体合金区域。 一次性栅极间隔物随后被选择性地移除到金属半导体合金区域。 沉积多孔或非多孔低k电介质材料以在栅极电极和源极和漏极区域之间提供低的寄生电容。 栅极电介质保持原始介电常数，因为一次性栅极间隔物可防止在高温过程中吸收额外的氧。
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公开(公告)号：US20090191679A1
公开(公告)日：2009-07-30
申请号：US12020916
申请日：2008-01-28
IPC分类号： H01L21/8236
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation.
摘要翻译： 在PFET栅极和NFET栅极上形成第一电介质层，并且被光刻图案化以在覆盖NFET区域的同时暴露PFET区域。 暴露的PFET有源区被蚀刻并用SiGe合金重新填充，SiGe合金向PFET通道施加单轴压应力。 第二电介质层形成在PFET栅极和NFET栅极上，并且被光刻图案化以暴露NFET区域，同时覆盖PFET区域。 暴露的NFET有源区被蚀刻并用硅 - 碳合金重新填充，硅 - 碳合金对NFET通道施加单轴拉伸应力。 可以通过原位掺杂或通过离子注入将掺杂剂引入到SiGe和硅 - 碳区域中。
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公开(公告)号：US20090174002A1
公开(公告)日：2009-07-09
申请号：US11971437
申请日：2008-01-09
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： Source and drain extension regions are selectively removed by a dopant concentration dependent etch or a doping type dependent etch, and an embedded stress-generating material such as SiGe alloy or a Si:C alloy in the source and drain extension regions is grown on a semiconductor substrate. The embedded stress-generating material may be grown only in the source and drain extension regions, or in the source and drain extension regions and in deep source and drain regions. In one embodiment, an etch process that removes doped semiconductor regions of one conductivity type selective to doped semiconductor regions of another conductivity type may be employed. In another embodiment, a dopant concentration dependent etch process that removes doped semiconductor regions irrespective of the conductivity type selective to undoped semiconductor regions may be employed.
摘要翻译： 源极和漏极延伸区域通过掺杂剂浓度依赖性蚀刻或掺杂型依赖性蚀刻被选择性去除，并且在源极和漏极延伸区域中嵌入的应力产生材料如SiGe合金或Si：C合金生长在半导体 基质。 嵌入的应力产生材料可以仅在源极和漏极延伸区域中，或者在源极和漏极延伸区域以及深的源极和漏极区域中生长。 在一个实施例中，可以采用去除对另一种导电类型的掺杂半导体区域有选择性的一种导电类型的掺杂半导体区域的蚀刻工艺。 在另一个实施例中，可以采用去除掺杂半导体区域而不考虑对未掺杂的半导体区域有选择性的导电类型的掺杂浓度依赖蚀刻工艺。
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公开(公告)号：US20090108300A1
公开(公告)日：2009-04-30
申请号：US11923131
申请日：2007-10-24
IPC分类号： H01L29/737
CPC分类号： H01L29/7371 , H01L29/0826 , H01L29/161
摘要： Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
摘要翻译： 公开了具有窄的基本上无间隙的SIC基座的改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管）的设计结构，其具有极小的外部基极的重叠。 此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。 因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。
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公开(公告)号：US07511317B2
公开(公告)日：2009-03-31
申请号：US11423286
申请日：2006-06-09
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Kathryn T. Schonenberg , Thomas A. Wallner
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Kathryn T. Schonenberg , Thomas A. Wallner
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L29/16 , H01L29/66242 , H01L29/7371
摘要： A method of forming an isolation region using porous silicon and a related structure are disclosed. One embodiment of the method may include forming a collector region; forming a porous silicon region in the collector region; forming a crystalline silicon intrinsic base layer over the collector region, the intrinsic base layer extending over a portion of the porous silicon region to form an extrinsic base; and forming an isolation region in the porous silicon region. The method is applicable to forming an HBT having a structure including a crystalline silicon intrinsic base extending beyond a collector region and extending over an isolation region to form a continuous intrinsic-to-extrinsic base conduction path of low resistance. The HBT has improved performance by having a smaller collector to intrinsic base interface and larger intrinsic base to extrinsic base interface.
摘要翻译： 公开了使用多孔硅形成隔离区域的方法和相关结构。 该方法的一个实施例可以包括形成收集区域; 在集电区域形成多孔硅区域; 在所述集电极区上形成晶体硅本征基极层，所述本征基极层在所述多孔硅区域的一部分上延伸以形成外部基极; 以及在所述多孔硅区域中形成隔离区域。 该方法适用于形成具有包括结晶硅本征基底的结构的HBT，该晶体硅本征基极延伸超过集电极区域并在隔离区域上延伸以形成具有低电阻的连续本征 - 外在的基极传导路径。 HBT通过使内部基本接口具有较小的集电极和较大的内在基极到外部基极接口来提高性能。
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公开(公告)号：US06977398B2
公开(公告)日：2005-12-20
申请号：US10819732
申请日：2004-04-07
IPC分类号： H01L21/265 , H01L21/331 , H01L21/8222 , H01L27/082 , H01L29/10 , H01L29/737 , H01L31/0328
CPC分类号： H01L29/7378 , H01L21/26506 , H01L29/1004 , H01L29/1012 , H01L29/66242 , H01L29/66318
摘要： A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.
摘要翻译： 提供了一种改善SiGe双极性产率以及制造SiGe异质结双极晶体管的方法。 本发明的方法包括将碳C离子注入到器件的以下区域之一：集电极区域，子集电极区域，非本征基极区域和集电极 - 基极结区域。 在优选实施例中，上述每个区域包括C植入物。
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10.发明申请REDUCED PATTERN LOADING FOR DOPED EPITAXIAL PROCESS AND SEMICONDUCTOR STRUCTURE 失效用于掺杂外延工艺和半导体结构的减少图案加载公开(公告)号：US20120248436A1
公开(公告)日：2012-10-04
申请号：US13075450
申请日：2011-03-30
CPC分类号： H01L21/823425 , H01L21/02529 , H01L21/02576 , H01L21/823412 , H01L22/12 , H01L22/34 , H01L29/66636 , H01L29/7848
摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.
摘要翻译： 提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。 第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。 第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。 第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。
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