公开(公告)号：US08294042B2

公开(公告)日：2012-10-23

申请号：US12844109

申请日：2010-07-27

申请人： Chang-Ming Lee ,  Wen-Fang Liu ,  Shih-Jung Huang ,  Ling-Kai Su

发明人： Chang-Ming Lee ,  Wen-Fang Liu ,  Shih-Jung Huang ,  Ling-Kai Su

IPC分类号： H01R9/00 ,  H05K7/00 ,  H05K1/11

CPC分类号： H05K3/4092 ,  H05K3/4007 ,  H05K2201/0311 ,  Y10T29/49204

摘要： A method of manufacturing a connector is provided. Firstly, a substrate having a first surface, a second surface opposite to the first surface and a through hole is provided. Next, a first conductive layer covering the inside wall of the through hole is formed on the substrate. Then, a filler is filled in the through hole to form a filler post. Next, a conductive elastic cantilever is formed over the first surface and electrically connected to the first conductive layer. Then, a gold layer is formed on the conductive elastic cantilever and over the first surface. A solder ball electrically connected to the first conductive layer is formed over the second surface.

摘要翻译： 提供一种制造连接器的方法。 首先，提供具有第一表面，与第一表面相对的第二表面和通孔的基板。 接着，在基板上形成覆盖贯通孔的内壁的第一导电层。 然后，在通孔中填充填料以形成填料柱。 接下来，在第一表面上形成导电弹性悬臂，并电连接到第一导电层。 然后，在导电弹性悬臂上形成金层，并在第一表面上形成金层。 电连接到第一导电层的焊球形成在第二表面上。

公开(公告)号：US08318411B2

公开(公告)日：2012-11-27

申请号：US12837462

申请日：2010-07-15

申请人： Chang-Ming Lee ,  Wen-Fang Liu ,  Shih-Jung Huang ,  Ling-Kai Su

发明人： Chang-Ming Lee ,  Wen-Fang Liu ,  Shih-Jung Huang ,  Ling-Kai Su

IPC分类号： G03F7/26

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for fabricating an interposer is provided. A substrate is provided having thereon at least a conductive via and at least a flange. The flange is bonded on the substrate and shades a portion of the via. A photoresist layer is formed on the interior surface of the via, on a contact surface of the flange and on an inner surface of the flange opposite to the contact surface. An opening is formed in the photoresist layer to expose a portion of the contact surface of the flange, while the photoresist layer still covers the interior surface of the via and the inner surface of the flange. A plating layer is formed on the exposed contact surface of the flange. The photoresist layer is then removed.

摘要翻译： 提供了一种制造插入件的方法。 设置有至少具有导电通孔和至少凸缘的衬底。 法兰结合在基板上并遮蔽通孔的一部分。 在通孔的内表面上，在凸缘的接触表面和与接触表面相对的凸缘的内表面上形成光致抗蚀剂层。 在光致抗蚀剂层中形成开口以暴露凸缘的接触表面的一部分，而光致抗蚀剂层仍然覆盖通孔的内表面和凸缘的内表面。 在凸缘的暴露的接触表面上形成镀层。 然后除去光致抗蚀剂层。

公开(公告)号：US20120024584A1

公开(公告)日：2012-02-02

申请号：US12844109

申请日：2010-07-27

申请人： Chang-Ming Lee ,  Wen-Fang Liu ,  Shih-Jung Huang ,  Ling-Kai Su

发明人： Chang-Ming Lee ,  Wen-Fang Liu ,  Shih-Jung Huang ,  Ling-Kai Su

IPC分类号： H05K1/11 ,  H01R43/16

CPC分类号： H05K3/4092 ,  H05K3/4007 ,  H05K2201/0311 ,  Y10T29/49204

摘要： A method of manufacturing a connector is provided. Firstly, a substrate having a first surface, a second surface opposite to the first surface and a through hole is provided. Next, a first conductive layer covering the inside wall of the through hole is formed on the substrate. Then, a filler is filled in the through hole to form a filler post. Next, a conductive elastic cantilever is formed over the first surface and electrically connected to the first conductive layer. Then, a gold layer is formed on the conductive elastic cantilever and over the first surface. A solder ball electrically connected to the first conductive layer is formed over the second surface.

摘要翻译： 提供一种制造连接器的方法。 首先，提供具有第一表面，与第一表面相对的第二表面和通孔的基板。 接着，在基板上形成覆盖贯通孔的内壁的第一导电层。 然后，在通孔中填充填料以形成填料柱。 接下来，在第一表面上形成导电弹性悬臂，并电连接到第一导电层。 然后，在导电弹性悬臂上形成金层，并在第一表面上形成金层。 电连接到第一导电层的焊球形成在第二表面上。

公开(公告)号：US20120015304A1

公开(公告)日：2012-01-19

申请号：US12837462

申请日：2010-07-15

申请人： Chang-Ming Lee ,  Wen-Fang Liu ,  Shih-Jung Huang ,  Ling-Kai Su

发明人： Chang-Ming Lee ,  Wen-Fang Liu ,  Shih-Jung Huang ,  Ling-Kai Su

IPC分类号： G03F7/20 ,  B05D5/12

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for fabricating an interposer is provided. A substrate is provided having thereon at least a conductive via and at least a flange. The flange is bonded on the substrate and shades a portion of the via. A photoresist layer is formed on the interior surface of the via, on a contact surface of the flange and on an inner surface of the flange opposite to the contact surface. An opening is formed in the photoresist layer to expose a portion of the contact surface of the flange, while the photoresist layer still covers the interior surface of the via and the inner surface of the flange. A plating layer is formed on the exposed contact surface of the flange. The photoresist layer is then removed.

摘要翻译： 提供了一种制造插入件的方法。 设置有至少具有导电通孔和至少凸缘的衬底。 法兰结合在基板上并遮蔽通孔的一部分。 在通孔的内表面上，在凸缘的接触表面和与接触表面相对的凸缘的内表面上形成光致抗蚀剂层。 在光致抗蚀剂层中形成开口以暴露凸缘的接触表面的一部分，而光致抗蚀剂层仍然覆盖通孔的内表面和凸缘的内表面。 在凸缘的暴露的接触表面上形成镀层。 然后除去光致抗蚀剂层。

公开(公告)号：US08598463B2

公开(公告)日：2013-12-03

申请号：US13050009

申请日：2011-03-17

申请人： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

发明人： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC分类号： H05K1/00 ,  C23C18/16

CPC分类号： H05K3/12 ,  C23C18/1605 ,  C23C18/165 ,  C25D5/022 ,  H05K1/0203 ,  H05K1/056 ,  H05K3/02 ,  H05K3/181 ,  H05K3/188 ,  H05K3/3436 ,  H05K2201/0187 ,  Y10T29/302 ,  Y10T29/49155 ,  Y10T156/10

摘要： A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.

摘要翻译： 电路板包括金属图案层，导热板，电绝缘层和至少一个电绝缘材料。 导热板具有平面。 电绝缘层设置在金属图案层和平面之间并且部分覆盖平面。 电绝缘材料覆盖未被电绝缘层覆盖并接触导热板的平面。 电绝缘层暴露电绝缘材料，并且电绝缘材料的热导率大于电绝缘层的热导率。

公开(公告)号：US20120031651A1

公开(公告)日：2012-02-09

申请号：US12944275

申请日：2010-11-11

申请人： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

发明人： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC分类号： H05K1/02 ,  H05K1/18

CPC分类号： H05K1/0203 ,  H05K1/056 ,  H05K3/3436 ,  H05K2201/0187 ,  H05K2201/10106

摘要： A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material.

摘要翻译： 提供了包括电路层，导热基板，绝缘层和至少一种导热材料的电路板。 导热基板具有平面。 绝缘层设置在电路层和平面之间，并部分覆盖平面。 导热材料覆盖该平面而不被绝缘层覆盖，并与导热基板接触。 绝缘层暴露导热材料。

公开(公告)号：US08161638B2

公开(公告)日：2012-04-24

申请号：US12783806

申请日：2010-05-20

申请人： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

发明人： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC分类号： H01K3/10

CPC分类号： H05K3/465 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/184 ,  H05K3/421 ,  H05K3/4661 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1056

摘要： A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.

摘要翻译： 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。

公开(公告)号：US20110100543A1

公开(公告)日：2011-05-05

申请号：US12783806

申请日：2010-05-20

申请人： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

发明人： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC分类号： B32B38/10 ,  B32B38/04

CPC分类号： H05K3/465 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/184 ,  H05K3/421 ,  H05K3/4661 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1056

摘要： A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.

摘要翻译： 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。

公开(公告)号：US20120031652A1

公开(公告)日：2012-02-09

申请号：US13050009

申请日：2011-03-17

申请人： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

发明人： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC分类号： H05K1/00 ,  C25D5/02 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12

CPC分类号： H05K3/12 ,  C23C18/1605 ,  C23C18/165 ,  C25D5/022 ,  H05K1/0203 ,  H05K1/056 ,  H05K3/02 ,  H05K3/181 ,  H05K3/188 ,  H05K3/3436 ,  H05K2201/0187 ,  Y10T29/302 ,  Y10T29/49155 ,  Y10T156/10

摘要： A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.

摘要翻译： 电路板包括金属图案层，导热板，电绝缘层和至少一个电绝缘材料。 导热板具有平面。 电绝缘层设置在金属图案层和平面之间并且部分覆盖平面。 电绝缘材料覆盖未被电绝缘层覆盖并接触导热板的平面。 电绝缘层暴露电绝缘材料，并且电绝缘材料的热导率大于电绝缘层的热导率。

公开(公告)号：US08288662B2

公开(公告)日：2012-10-16

申请号：US12718194

申请日：2010-03-05

申请人： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

发明人： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC分类号： H05K1/11

CPC分类号： H05K3/184 ,  H05K3/0032 ,  H05K3/387 ,  H05K3/421 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2203/107 ,  H05K2203/1173

摘要： A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.

摘要翻译： 提供了包括电路板，绝缘层，导电通孔，可镀介电层和导电图案的电路结构。 绝缘层设置在电路板上并覆盖电路板的电路层。 导电通孔穿过绝缘层并连接电路层并从绝缘层的表面突出。 具有沟槽图案的可镀介电层设置在绝缘层的表面上，其中从表面突出的导电通孔的部分位于沟槽图案中。 可镀介电层的材料包括化学镀层材料。 导电图案处于沟槽图案中并且连接导电通孔，其中在导电图案和导电通孔之间存在界面，并从绝缘层的表面突出。