中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.024 seconds)

    Circuit structure and manufacturing method thereof
    1.
    发明授权
    Circuit structure and manufacturing method thereof 有权
    电路结构及其制造方法

    公开(公告)号：US08987608B2

    公开(公告)日：2015-03-24

    申请号：US13615722

    申请日：2012-09-14

    Applicant: Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

    Inventor： Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

    IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

    CPC classification number: H05K1/0221 ,  H05K3/4644 ,  Y10T29/49155

    Abstract: A circuit structure includes an inner circuit layer, a first and a second dielectric layers, a first and a second conductive material layers, and a second and a third conductive layers. The first dielectric layer covers a first conductive layer of the inner circuit layer and has a first surface and first circuit grooves. The first conductive material layer is disposed inside the first circuit grooves. The second conductive layer is disposed on the first surface and includes a signal trace and at least two reference traces. The second dielectric layer covers the first surface and the second conductive layer and has a second surface and second circuit grooves. Widths of the first and the second circuit grooves are smaller than that of the reference traces. The second conductive material layer is disposed inside the second circuit grooves. The third conductive layer is disposed on the second surface.

    Abstract translation: 电路结构包括内部电路层，第一和第二电介质层，第一和第二导电材料层以及第二和第三导电层。 第一电介质层覆盖内电路层的第一导电层，并具有第一表面和第一电路槽。 第一导电材料层设置在第一电路槽的内部。 第二导电层设置在第一表面上并且包括信号迹线和至少两个参考迹线。 第二电介质层覆盖第一表面和第二导电层，并具有第二表面和第二电路槽。 第一和第二电路槽的宽度小于参考轨迹的宽度。 第二导电材料层设置在第二电路槽的内部。 第三导电层设置在第二表面上。

    Embedded wiring board and method for manufacturing the same
    3.
    发明授权
    Embedded wiring board and method for manufacturing the same 有权
    嵌入式布线板及其制造方法

    公开(公告)号：US08373071B2

    公开(公告)日：2013-02-12

    申请号：US12696629

    申请日：2010-01-29

    Applicant: Cheng-Po Yu ,  Chai-Liang Hsu

    Inventor： Cheng-Po Yu ,  Chai-Liang Hsu

    IPC: H05K1/00

    CPC classification number: H05K3/107 ,  H05K3/181 ,  H05K3/422 ,  H05K2201/0376

    Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed, in which the activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

    Abstract translation: 提供了一种用于制造嵌入式布线板的方法。 形成激活绝缘层，其中活化绝缘层包括多个催化剂颗粒，并覆盖第一布线层。 在活化绝缘层上形成凹版图案和部分露出第一布线层的至少一个盲孔，其中一些催化剂颗粒被活化并以凹版图案和盲孔曝光。 将激活绝缘层浸入第一化学镀溶液中，并通过化学镀在盲孔中形成固体导电柱。 在形成固体导电柱之后，将激活绝缘层浸入第二化学镀溶液中，并且通过无电解电镀在凹版图案中形成第二布线层。 第一化学镀液和第二化学镀液的成分不同。

    Method for forming embedded circuit
    4.
    发明授权
    Method for forming embedded circuit 失效
    嵌入式电路的形成方法

    公开(公告)号：US08171626B1

    公开(公告)日：2012-05-08

    申请号：US13155375

    申请日：2011-06-07

    Applicant: Cheng-Po Yu ,  Chi-Min Chang

    Inventor： Cheng-Po Yu ,  Chi-Min Chang

    IPC: H05K3/02 ,  H05K3/10 ,  H05K3/00 ,  H01R9/00 ,  H01R43/00

    CPC classification number: H05K3/465 ,  H05K3/107 ,  H05K2201/0347 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49155

    Abstract: A method for forming an embedded circuit is disclosed. First, a substrate including a dielectric layer is provided. Second, the dielectric layer is entirely covered by a dummy layer. Then, the dummy layer is patterned and a trench is formed in the dielectric layer at the same time. Later, a seed layer is formed to entirely cover the dummy layer and the trench. Next, the dummy layer is removed and the seed layer covering the dummy layer is removed, too. Afterwards, a metal layer is filled in the trench to form an embedded circuit embedded in the dielectric layer.

    Abstract translation: 公开了一种用于形成嵌入式电路的方法。 首先，提供包括电介质层的基板。 第二，介电层完全被虚拟层覆盖。 然后，对虚拟层进行图案化，同时在电介质层中形成沟槽。 之后，形成种子层以完全覆盖虚设层和沟槽。 接下来，去除虚拟层，并且去除覆盖虚拟层的种子层。 之后，在沟槽中填充金属层，形成嵌入电介质层的嵌入电路。

    CIRCUIT BOARD
    5.
    发明申请
    CIRCUIT BOARD 审中-公开
    电路板

    公开(公告)号：US20120031651A1

    公开(公告)日：2012-02-09

    申请号：US12944275

    申请日：2010-11-11

    Applicant: TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/02 ,  H05K1/18

    CPC classification number: H05K1/0203 ,  H05K1/056 ,  H05K3/3436 ,  H05K2201/0187 ,  H05K2201/10106

    Abstract: A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material.

    Abstract translation: 提供了包括电路层，导热基板，绝缘层和至少一种导热材料的电路板。 导热基板具有平面。 绝缘层设置在电路层和平面之间，并部分覆盖平面。 导热材料覆盖该平面而不被绝缘层覆盖，并与导热基板接触。 绝缘层暴露导热材料。

    Method of fabricating substrate
    6.
    发明授权
    Method of fabricating substrate 有权
    制造基板的方法

    公开(公告)号：US07867908B2

    公开(公告)日：2011-01-11

    申请号：US12422428

    申请日：2009-04-13

    Applicant: Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    Inventor： Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    IPC: H01L21/302

    CPC classification number: H01L23/142 ,  H01L21/6835 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/202 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.

    Abstract translation: 制造衬底的方法包括以下步骤。 首先，提供具有第一表面和第二表面的金属板。 执行第一半蚀刻工艺以将金属板的第一表面蚀刻到第一深度，使得在第一表面上形成第一图案化金属层。 接下来，将第一绝缘材料沉积在第一图案化金属层中的间隙中以形成第一绝缘体。 此后，执行第二半蚀刻工艺以将金属板的第二表面蚀刻到第二深度并且暴露第一绝缘体的至少一部分，使得在第二表面上形成第二图案化金属层。 第一深度和第二深度一起等于金属面板的厚度。

    METHOD FOR FORMING CIRCUIT BOARD STRUCTURE OF COMPOSITE MATERIAL
    8.
    发明申请
    METHOD FOR FORMING CIRCUIT BOARD STRUCTURE OF COMPOSITE MATERIAL 审中-公开
    形成复合材料电路板结构的方法

    公开(公告)号：US20100266752A1

    公开(公告)日：2010-10-21

    申请号：US12763224

    申请日：2010-04-20

    Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Wen-Fang Liu

    Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Wen-Fang Liu

    IPC: H05K3/10

    CPC classification number: H05K3/107 ,  H05K1/036 ,  H05K1/0373 ,  H05K3/181 ,  H05K3/184 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2201/0257 ,  H05K2203/0264 ,  H05K2203/107 ,  H05K2203/308

    Abstract: A method for forming a circuit board structure of composite material is disclosed. First, a composite material structure including a substrate and a composite material dielectric layer is provided. The composite material dielectric layer includes a catalyst dielectric layer contacting the substrate and at least one sacrificial layer contacting the catalyst dielectric layer. The sacrificial layer is insoluble in water. Later, the composite material dielectric layer is patterned and simultaneously catalyst particles are activated. Then, a conductive layer is formed on the activated catalyst particles. Afterwards, at least one sacrificial layer is removed.

    Abstract translation: 公开了一种形成复合材料的电路板结构的方法。 首先，提供包括基板和复合材料介电层的复合材料结构。 复合材料介电层包括与基底接触的催化剂介电层和与催化剂介电层接触的至少一个牺牲层。 牺牲层不溶于水。 之后，复合材料介电层被图案化，同时催化剂颗粒被激活。 然后，在活化的催化剂颗粒上形成导电层。 之后，去除至少一个牺牲层。

Patent Agency Ranking