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公开(公告)号：US08161638B2
公开(公告)日：2012-04-24
申请号：US12783806
申请日：2010-05-20
申请人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
发明人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
IPC分类号： H01K3/10
CPC分类号： H05K3/465 , H05K3/0032 , H05K3/0035 , H05K3/184 , H05K3/421 , H05K3/4661 , H05K2201/0166 , H05K2201/0195 , H05K2203/1152 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1056
摘要： A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.
摘要翻译： 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。
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公开(公告)号：US20110100543A1
公开(公告)日：2011-05-05
申请号：US12783806
申请日：2010-05-20
申请人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
发明人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC分类号： H05K3/465 , H05K3/0032 , H05K3/0035 , H05K3/184 , H05K3/421 , H05K3/4661 , H05K2201/0166 , H05K2201/0195 , H05K2203/1152 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1056
摘要： A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.
摘要翻译： 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。
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公开(公告)号：US08598463B2
公开(公告)日：2013-12-03
申请号：US13050009
申请日：2011-03-17
申请人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
发明人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC分类号： H05K3/12 , C23C18/1605 , C23C18/165 , C25D5/022 , H05K1/0203 , H05K1/056 , H05K3/02 , H05K3/181 , H05K3/188 , H05K3/3436 , H05K2201/0187 , Y10T29/302 , Y10T29/49155 , Y10T156/10
摘要： A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.
摘要翻译： 电路板包括金属图案层，导热板，电绝缘层和至少一个电绝缘材料。 导热板具有平面。 电绝缘层设置在金属图案层和平面之间并且部分覆盖平面。 电绝缘材料覆盖未被电绝缘层覆盖并接触导热板的平面。 电绝缘层暴露电绝缘材料，并且电绝缘材料的热导率大于电绝缘层的热导率。
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公开(公告)号：US20120031651A1
公开(公告)日：2012-02-09
申请号：US12944275
申请日：2010-11-11
申请人： TZYY-JANG TSENG , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
发明人： TZYY-JANG TSENG , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC分类号： H05K1/0203 , H05K1/056 , H05K3/3436 , H05K2201/0187 , H05K2201/10106
摘要： A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material.
摘要翻译： 提供了包括电路层，导热基板，绝缘层和至少一种导热材料的电路板。 导热基板具有平面。 绝缘层设置在电路层和平面之间，并部分覆盖平面。 导热材料覆盖该平面而不被绝缘层覆盖，并与导热基板接触。 绝缘层暴露导热材料。
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公开(公告)号：US08288662B2
公开(公告)日：2012-10-16
申请号：US12718194
申请日：2010-03-05
申请人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
发明人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
IPC分类号： H05K1/11
CPC分类号： H05K3/184 , H05K3/0032 , H05K3/387 , H05K3/421 , H05K3/465 , H05K3/4661 , H05K2201/0195 , H05K2201/0347 , H05K2203/107 , H05K2203/1173
摘要： A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.
摘要翻译： 提供了包括电路板，绝缘层，导电通孔，可镀介电层和导电图案的电路结构。 绝缘层设置在电路板上并覆盖电路板的电路层。 导电通孔穿过绝缘层并连接电路层并从绝缘层的表面突出。 具有沟槽图案的可镀介电层设置在绝缘层的表面上，其中从表面突出的导电通孔的部分位于沟槽图案中。 可镀介电层的材料包括化学镀层材料。 导电图案处于沟槽图案中并且连接导电通孔，其中在导电图案和导电通孔之间存在界面，并从绝缘层的表面突出。
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公开(公告)号：US08247705B2
公开(公告)日：2012-08-21
申请号：US12718226
申请日：2010-03-05
申请人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
发明人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
IPC分类号： H05K1/11
CPC分类号： H05K3/387 , C23C18/1653 , H05K3/4644 , H05K2201/0129 , H05K2201/0145 , H05K2201/0154 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322
摘要： A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.
摘要翻译： 电路基板的制造方法包括以下步骤。 在基板的至少一个表面上形成介电层。 在电介质层上形成绝缘层。 去除绝缘层的一部分和电介质层的一部分，以在电介质层和绝缘层中形成至少一个盲孔。 在盲通孔的侧壁和绝缘层的剩余部分上形成化学镀层，其中绝缘层和化学镀层之间的结合强度大于介电层和化学镀层之间的结合强度。 电镀图案化导电层以覆盖化学镀层。
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公开(公告)号：US20110155427A1
公开(公告)日：2011-06-30
申请号：US12718226
申请日：2010-03-05
申请人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
发明人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC分类号： H05K3/387 , C23C18/1653 , H05K3/4644 , H05K2201/0129 , H05K2201/0145 , H05K2201/0154 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322
摘要： A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.
摘要翻译： 电路基板的制造方法包括以下步骤。 在基板的至少一个表面上形成介电层。 在电介质层上形成绝缘层。 去除绝缘层的一部分和电介质层的一部分，以在电介质层和绝缘层中形成至少一个盲孔。 在盲通孔的侧壁和绝缘层的剩余部分上形成化学镀层，其中绝缘层和化学镀层之间的结合强度大于介电层和化学镀层之间的结合强度。 电镀图案化导电层以覆盖化学镀层。
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公开(公告)号：US20110094779A1
公开(公告)日：2011-04-28
申请号：US12718194
申请日：2010-03-05
申请人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
发明人： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC分类号： H05K3/184 , H05K3/0032 , H05K3/387 , H05K3/421 , H05K3/465 , H05K3/4661 , H05K2201/0195 , H05K2201/0347 , H05K2203/107 , H05K2203/1173
摘要： A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.
摘要翻译： 提供了包括电路板，绝缘层，导电通孔，可镀介电层和导电图案的电路结构。 绝缘层设置在电路板上并覆盖电路板的电路层。 导电通孔穿过绝缘层并连接电路层并从绝缘层的表面突出。 具有沟槽图案的可镀介电层设置在绝缘层的表面上，其中从表面突出的导电通孔的部分位于沟槽图案中。 可镀介电层的材料包括化学镀层材料。 导电图案处于沟槽图案中并且连接导电通孔，其中在导电图案和导电通孔之间存在界面，并从绝缘层的表面突出。
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公开(公告)号：US20120031652A1
公开(公告)日：2012-02-09
申请号：US13050009
申请日：2011-03-17
申请人： TZYY-JANG TSENG , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
发明人： TZYY-JANG TSENG , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC分类号： H05K3/12 , C23C18/1605 , C23C18/165 , C25D5/022 , H05K1/0203 , H05K1/056 , H05K3/02 , H05K3/181 , H05K3/188 , H05K3/3436 , H05K2201/0187 , Y10T29/302 , Y10T29/49155 , Y10T156/10
摘要： A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.
摘要翻译： 电路板包括金属图案层，导热板，电绝缘层和至少一个电绝缘材料。 导热板具有平面。 电绝缘层设置在金属图案层和平面之间并且部分覆盖平面。 电绝缘材料覆盖未被电绝缘层覆盖并接触导热板的平面。 电绝缘层暴露电绝缘材料，并且电绝缘材料的热导率大于电绝缘层的热导率。
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公开(公告)号：US20100266752A1
公开(公告)日：2010-10-21
申请号：US12763224
申请日：2010-04-20
申请人： Tzyy-Jang Tseng , Cheng-Po Yu , Wen-Fang Liu
发明人： Tzyy-Jang Tseng , Cheng-Po Yu , Wen-Fang Liu
IPC分类号： H05K3/10
CPC分类号： H05K3/107 , H05K1/036 , H05K1/0373 , H05K3/181 , H05K3/184 , H05K3/185 , H05K2201/0236 , H05K2201/0257 , H05K2203/0264 , H05K2203/107 , H05K2203/308
摘要： A method for forming a circuit board structure of composite material is disclosed. First, a composite material structure including a substrate and a composite material dielectric layer is provided. The composite material dielectric layer includes a catalyst dielectric layer contacting the substrate and at least one sacrificial layer contacting the catalyst dielectric layer. The sacrificial layer is insoluble in water. Later, the composite material dielectric layer is patterned and simultaneously catalyst particles are activated. Then, a conductive layer is formed on the activated catalyst particles. Afterwards, at least one sacrificial layer is removed.
摘要翻译： 公开了一种形成复合材料的电路板结构的方法。 首先，提供包括基板和复合材料介电层的复合材料结构。 复合材料介电层包括与基底接触的催化剂介电层和与催化剂介电层接触的至少一个牺牲层。 牺牲层不溶于水。 之后，复合材料介电层被图案化，同时催化剂颗粒被激活。 然后，在活化的催化剂颗粒上形成导电层。 之后，去除至少一个牺牲层。
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