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    METAL RESISTOR, RESISTOR MATERIAL AND METHOD
    1.
    发明申请
    METAL RESISTOR, RESISTOR MATERIAL AND METHOD 失效
    金属电阻器，电阻材料和方法

    公开(公告)号：US20080030298A1

    公开(公告)日：2008-02-07

    申请号：US11869218

    申请日：2007-10-09

    申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Shyng-Tsong Cheng

    发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Shyng-Tsong Cheng

    IPC分类号： H01C1/012

    CPC分类号： H01L29/86 ,  H01L23/5228 ,  H01L2924/0002 ,  H04W36/08 ,  H04W88/08 ,  H04W88/18 ,  H01L2924/00

    摘要： A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The method is less complex than conventional processes, allows control of the resistance by the amount of infusion material infused, and is compatible with conventional BEOL processes.

    摘要翻译： 公开了一种金属电阻器和电阻器材料以及形成金属电阻器的方法。 金属电阻器可以包括从由以下组成的组中输入的输入金属：铜（Cu），其输入硅（Si），氮（N 2/2），碳（C），钽（ Ta），钛（Ti）和钨（W），以及输入硅（Si），氮（N 2/2），碳（C），钽（Ta），钛 （Ti）和钨（W）。 该方法比常规方法复杂得多，允许通过灌注材料的量控制电阻，并且与传统的BEOL方法兼容。

    INTERCONNECT STRUCTURE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD OF FABRICATING SAME
    5.
    发明申请
    INTERCONNECT STRUCTURE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD OF FABRICATING SAME 审中-公开
    具有改进的电阻率的互连结构及其制造方法

    公开(公告)号：US20090072406A1

    公开(公告)日：2009-03-19

    申请号：US11856970

    申请日：2007-09-18

    申请人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Kaushik Chanda

    发明人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Kaushik Chanda

    IPC分类号： H01L21/31

    CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect structure includes a metallic interfacial layer that is at least horizontally present at the bottom of an opening located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer does not form an alloy with an underlying conductive material that is embedded within the first dielectric material. In some embodiments of the present invention, the metallic interfacial layer is also present on exposed sidewalls of the second dielectric material that is located atop the first dielectric material. Atop the metallic interfacial layer there is present a diffusion barrier liner. In some embodiments, the diffusion barrier liner includes a lower layer of a metallic nitride and an upper layer of a metal. In accordance with the present invention, the metallic interfacial layer also does not form an alloy with any portion of the diffusion barrier liner.

    摘要翻译： 提供了一种互连结构，其中在不引入互连结构内的气蚀特征的情况下，其电迁移阻力得到改善。 互连结构包括金属界面层，其至少水平存在于位于第二介电材料内的开口的底部，该第二电介质材料位于第一电介质材料的顶部，该第一介电材料包括嵌入其中的第一导电材料。 金属界面层不与嵌入在第一介电材料内的下面的导电材料形成合金。 在本发明的一些实施例中，金属界面层也存在于位于第一介电材料顶部的第二介电材料的暴露的侧壁上。 在金属界面层顶部存在扩散阻挡层。 在一些实施例中，扩散阻挡衬里包括金属氮化物的下层和金属的上层。 根据本发明，金属界面层也不与扩散阻挡衬里的任何部分形成合金。

    SEMICONDUCTOR WIRING STRUCTURES INCLUDING DIELECTRIC CAP WITHIN METAL CAP LAYER
    6.
    发明申请
    SEMICONDUCTOR WIRING STRUCTURES INCLUDING DIELECTRIC CAP WITHIN METAL CAP LAYER 有权
    半导体接线结构包括金属盖层中的电介质盖

    公开(公告)号：US20080308942A1

    公开(公告)日：2008-12-18

    申请号：US11761495

    申请日：2007-06-12

    申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76865 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

    摘要翻译： 包括其中具有金属布线的电介质层，从金属布线向下延伸的孔，在金属布线上方的金属盖层和位于金属盖层的一部分内的局部电介质盖的半导体布线结构 公开了与金属布线的接触和相关方法。 局部电介质盖表示在双镶嵌互连的金属布线中有意创造的弱点，其在管线中引起电迁移（EM）空隙，而不是在从金属布线向下延伸的通孔的底部。 由于线路中的临界空隙尺寸失效，特别是金属盖层（衬垫）冗余度，远远大于通孔失效，所以EM寿命可以显着提高。

    METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR
    8.
    发明申请
    METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR 审中-公开
    在半导体中预测电介质破坏的方法

    公开(公告)号：US20060281338A1

    公开(公告)日：2006-12-14

    申请号：US11160213

    申请日：2005-06-14

    申请人： Kaushik Chanda ,  Hazara Rathore ,  Paul McLaughlin ,  Robert Edwards ,  Lawrence Clevenger ,  Andrew Cowley ,  Chih-Chao Yang ,  Conrad Barile

    发明人： Kaushik Chanda ,  Hazara Rathore ,  Paul McLaughlin ,  Robert Edwards ,  Lawrence Clevenger ,  Andrew Cowley ,  Chih-Chao Yang ,  Conrad Barile

    IPC分类号： H01L21/00

    CPC分类号： H01L22/14 ,  G01R31/2642 ,  G01R31/2831

    摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.

    摘要翻译： 本发明预测半导体中的过早的介质击穿。 对于半导体晶片计算至少一个绝缘击穿模式。 如果计算一种模式，则过早的介电击穿将与在所述计算模式中具有小于多个击穿电压的预定标准偏差的击穿电压的任何半导体相关联。 如果计算多个模式，则确定最准确地代表半导体晶片的电介质击穿的模式，并且过早的电介质击穿将与任何具有小于计算模式的预定标准的击穿电压的半导体相关联，其最准确地表示用于 半导体晶片。