公开(公告)号：US06968613B2

公开(公告)日：2005-11-29

申请号：US10176122

申请日：2002-06-20

申请人： Chung-Che Tsai ,  Jin-Chuan Bai

发明人： Chung-Che Tsai ,  Jin-Chuan Bai

IPC分类号： H05K3/28 ,  H01K3/10

CPC分类号： H05K3/28 ,  H05K2201/0959 ,  H05K2203/0582 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49171

摘要： A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed from the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.

摘要翻译： 提出了一种电路板的制造方法，其中芯层形成有多个导电迹线，并且将光致抗蚀剂分别施加在导电迹线的端子上。 然后，在芯层上施加不可焊接的材料以覆盖导电迹线，绝缘材料除外，并且不可焊接材料适于与绝缘材料表面齐平，从而使绝缘材料暴露 来自不可焊接材料。 最后，从芯层去除绝缘材料以露出导电迹线的端子，其中暴露的端子用作可焊接焊球，焊料凸块或接合线的接合焊盘或接合指状物。 该电路板通过简化的工艺成本有效地制造，并且有益于精确地暴露接合焊盘或接合指，从而显着提高制造的电路板的产量。

公开(公告)号：US06740540B2

公开(公告)日：2004-05-25

申请号：US10170664

申请日：2002-06-12

申请人： Chung-Che Tsai ,  Jin-Chuan Bai

发明人： Chung-Che Tsai ,  Jin-Chuan Bai

IPC分类号： H01L2144

CPC分类号： H05K3/28 ,  H05K2203/0264 ,  H05K2203/0278 ,  H05K2203/0582 ,  H05K2203/066 ,  Y10T29/49124

摘要： A fabrication method for a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is applied on terminals of the conductive traces. A non-solderable material is peelably applied over a support member, and attached to the core layer to cover the conductive traces, wherein adhesion between the support member and the non-solderable material is smaller than adhesion between the non-solderable material and the core layer. Then, the support member is peeled to expose the non-solderable material; further, the non-solderable material is partly removed to expose the photo resist. Finally, the photo resist is etched away to expose the terminals of the conductive traces. The exposed terminals serve as bond pads or fingers where solder balls, bumps or wires are bonded for electrical connection purpose.

摘要翻译： 提出了一种用于电路板的制造方法，其中芯层形成有多个导电迹线，并且光刻胶施加在导电迹线的端子上。 不可焊接材料可剥离地施加在支撑构件上，并且附接到芯层以覆盖导电迹线，其中支撑构件和不可焊接材料之间的粘附小于不可焊材料和芯之间的粘附 层。 然后，将支撑构件剥离以露出不可焊接材料; 此外，部分地去除不可焊接材料以暴露光致抗蚀剂。 最后，蚀刻光刻胶以露出导电迹线的端子。 露出的端子用作接合焊盘或手指，其中焊球，凸块或导线被接合用于电连接目的。

公开(公告)号：US20050062152A1

公开(公告)日：2005-03-24

申请号：US10671176

申请日：2003-09-24

申请人： Chung-Che Tsai

发明人： Chung-Che Tsai

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L21/565 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A window ball grid array (WBGA) semiconductor package and a fabrication method thereof are provided. This WBGA package includes: a substrate having a through opening; a chip mounted on an upper surface and over the opening of the substrate via an adhesive, and electrically connected to a lower surface of the substrate via bonding wires through the opening, with gaps, not applied with the adhesive, formed between the chip and the substrate; a first encapsulation body made of a resin material for encapsulating the chip and the bonding wires, allowing the resin material to pass through the gaps to fill the opening of the substrate and the gaps; a second encapsulation body for covering the part of the first encapsulation body on the lower surface of the substrate; and a plurality of solder balls bonded to area free of the second encapsulation body on the lower surface of the substrate.

摘要翻译： 提供了一种窗户球栅阵列（WBGA）半导体封装及其制造方法。 该WBGA封装包括：具有通孔的衬底; 通过粘合剂安装在基板的上表面和开口上方的芯片，并且通过接合线通过开口电连接到衬底的下表面，其中间隙形成在芯片和芯片之间， 基质; 由用于封装芯片和接合线的树脂材料制成的第一封装体，允许树脂材料通过间隙以填充基板的开口和间隙; 第二封装体，用于覆盖所述基板的下表面上的所述第一封装体的所述部分; 以及在衬底的下表面上接合到没有第二包封体的区域的多个焊球。

公开(公告)号：US06857865B2

公开(公告)日：2005-02-22

申请号：US10176145

申请日：2002-06-20

申请人： Chung-Che Tsai ,  Wei-Heng Shan

发明人： Chung-Che Tsai ,  Wei-Heng Shan

IPC分类号： B29C45/14 ,  B29C45/26 ,  B29C45/56 ,  H01L21/56

CPC分类号： H01L21/565 ,  B29C45/14655 ,  B29C45/14836 ,  B29C45/2602 ,  B29C45/56 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A mold structure for package fabrication is proposed, and includes a top mold, a fixture and a bottom mold. The top mold is formed with at least an upwardly recessed portion; the fixture is formed with a plurality of downwardly recessed portions; and the bottom mold has a recessed cavity for receiving the fixture therein, and adapted to be engaged with the top mold, wherein a resilient member is disposed on an inner wall of the recessed cavity, and interposed between the fixture and the recessed cavity of the bottom mold, allowing the resilient member to provide a resilient force for properly positioning the fixture. By using the above mold structure, chips mounted on a substrate can be firmly supported in the mold structure without causing chip cracks during a molding process for encapsulating the chips.

摘要翻译： 提出了一种用于封装制造的模具结构，包括顶模，夹具和底模。 顶模形成有至少一个向上凹入的部分; 夹具形成有多个向下凹陷部分; 并且底模具有用于在其中容纳固定件的凹腔，并且适于与顶模接合，其中弹性构件设置在凹腔的内壁上，并且插入在固定件与凹部的凹腔之间 底部模具，允许弹性构件提供用于适当地定位固定装置的弹性力。 通过使用上述模具结构，可以在模具结构中牢固地支撑安装在基板上的芯片，而不会在用于封装芯片的模制过程中引起芯片裂纹。

公开(公告)号：US06849915B1

公开(公告)日：2005-02-01

申请号：US10649847

申请日：2003-08-26

申请人： Chung-Che Tsai

发明人： Chung-Che Tsai

IPC分类号： H01L21/00 ,  H01L31/0203 ,  H01L31/0232

CPC分类号： H01L31/0203 ,  H01L31/02325 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： A light sensitive semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a chip carrier and encompassed by a dam, and an infrared filter is attached to the dam to hermetically isolate the chip from the atmosphere. An encapsulant is formed on the chip carrier and surrounds the dam, and a lens is supported by the encapsulant to be positioned above the infrared filter. This allows light to penetrate through the infrared filter and lens to reach the chip. Before forming the encapsulant and mounting the lens, the semi-fabricated package with the chip being hermetically isolated by the infrared filter and dam is subject to a leak test, allowing a semi-fabricated package successfully passing the test to be formed with the encapsulant and lens, so as to reduce fabrication costs and improve yield of fabricated package products.

摘要翻译： 提供了一种光敏半导体封装及其制造方法，其中芯片安装在芯片载体上并被堤坝包围，并且红外滤光器附接到坝以将芯片与大气隔离。 密封剂形成在芯片载体上并围绕坝，并且透镜由密封剂支撑以定位在红外滤光器上方。 这允许光穿过红外滤光镜和透镜到达芯片。 在形成密封剂并安装透镜之前，具有通过红外滤光器和阻流器密封隔离的芯片的半制成封装进行泄漏测试，允许半制成封装成功地通过使用密封剂形成的测试， 透镜，以便降低制造成本并提高制造的包装产品的产量。

公开(公告)号：US06326700B1

公开(公告)日：2001-12-04

申请号：US09639202

申请日：2000-08-15

申请人： Jinchuan Bai ,  Chung-Che Tsai

发明人： Jinchuan Bai ,  Chung-Che Tsai

IPC分类号： H01L2329

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A low-profile semiconductor device is disclosed which includes a substrate having a base layer formed with at least a hole and a plurality of conductive traces arranged on the base layer. A semiconductor die is attached to the base layer of the substrate opposite to the conductive traces and electrically connected to the conductive traces by a plurality of first conductive elements passing through the hole of the base layer. A plurality of second conductive elements are arrayedly connected to the terminal of each of the conductive traces for providing externally electrical connection to the semiconductor die. The semiconductor die is encapsulated by a first encapsulant formed on the surface of the substrate on which the semiconductor die is mounted. A second encapsulant is formed on the surface of the substrate on which the conductive traces are arranged to completely encapsulate the conductive traces, first conductive elements and the hole. Meanwhile, the second encapsulant is formed to encapsulate the second conductive elements in such a manner that the bottom ends of the second conductive elements are exposed to and flush with the bottom surface of the second encapsulant.

摘要翻译： 公开了一种低轮廓半导体器件，其包括具有至少形成有孔的基底层和布置在基底层上的多个导电迹线的基板。 半导体管芯附着到与导电迹线相对的基板的基底层，并且通过穿过基底层的孔的多个第一导电元件电连接到导电迹线。 多个第二导电元件阵列地连接到每个导电迹线的端子，以提供与半导体管芯的外部电连接。 半导体管芯由形成在其上安装半导体管芯的衬底的表面上的第一密封剂封装。 第二密封剂形成在衬底的表面上，导电迹线布置在其上以完全封装导电迹线，第一导电元件和孔。 同时，形成第二密封剂以使第二导电元件的底端暴露于第二密封剂的底表面并与其平齐的方式封装第二导电元件。

公开(公告)号：US20200168566A1

公开(公告)日：2020-05-28

申请号：US16237725

申请日：2019-01-01

申请人： Chung-Che Tsai

发明人： Chung-Che Tsai

IPC分类号： H01L23/66 ,  H01L23/552 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

摘要： A semiconductor package includes a substrate. At least a high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate surrounding the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring surrounding the high-frequency chip. A second ground ring is disposed on the top of the substrate surrounding the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring surrounding the circuit component. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.

公开(公告)号：US20050046003A1

公开(公告)日：2005-03-03

申请号：US10649884

申请日：2003-08-26

申请人： Chung-Che Tsai

发明人： Chung-Che Tsai

IPC分类号： H01L23/495 ,  H01L25/065 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L23/49575 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked-chip semiconductor package and a fabrication method thereof are provided in which a thermal blocking member is applied over an opening formed through a chip carrier, with a first chip being mounted on the thermal blocking member and a second chip being attached oppositely to the thermal blocking member and received within the opening; the first and second chips are electrically connected to the chip carrier by bonding wires. An encapsulant is formed on the chip carrier for encapsulating the second chip and having a cavity for receiving and exposing the first chip that is a light sensitive chip. By the thermal blocking member interposed between the first and second chips, heat produced from the second chip is prevented from passing to the first chip, thereby not damaging the first chip or causing warpage of the first chip, which can thus assure reliable performances of the semiconductor package.

摘要翻译： 提供了一种叠层芯片半导体封装及其制造方法，其中将热阻挡构件施加在通过芯片载体形成的开口上，第一芯片安装在热阻挡构件上，第二芯片与第二芯片相对地安装 热封件并在开口内接收; 第一芯片和第二芯片通过接合线电连接到芯片载体。 密封剂形成在芯片载体上，用于封装第二芯片并且具有用于接收和暴露作为光敏芯片的第一芯片的空腔。 通过插入在第一和第二芯片之间的热阻挡件，防止从第二芯片产生的热量传递到第一芯片，从而不会损坏第一芯片或引起第一芯片的翘曲，从而可以确保第一芯片的可靠性能 半导体封装。

公开(公告)号：US06713857B1

公开(公告)日：2004-03-30

申请号：US10314064

申请日：2002-12-05

申请人： Chung-Che Tsai

发明人： Chung-Che Tsai

IPC分类号： H01L2302

CPC分类号： H01L21/568 ,  H01L23/055 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L31/0203 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A stacked multi-chip semiconductor package and a fabrication method thereof are provided. A chip carrier is formed with an opening for receiving a first chip therein, and a second chip is stacked on the first chip and over the opening, wherein the first and second chips are respectively electrically connected to the chip carrier by bonding wires. A first encapsulant is formed to encapsulate first chip and corresponding bonding wires, and a second encapsulant is formed around the second chip to encompass a cavity for receiving the second chip and corresponding bonding wires therein. A lid is attached to the second encapsulant for covering the cavity. This semiconductor package allows high integration and increase in operational performances by virtue of stacked multi-chip structure.

摘要翻译： 提供一种叠层多芯片半导体封装及其制造方法。 芯片载体形成有用于在其中接收第一芯片的开口，并且第二芯片堆叠在第一芯片上并在开口上方，其中第一芯片和第二芯片通过接合线分别电连接到芯片载体。 第一密封剂被形成以封装第一芯片和相应的接合线，并且第二密封剂围绕第二芯片形成以包围用于接收第二芯片的空腔和其中的对应的接合线。 盖子附接到第二密封剂以覆盖空腔。 这种半导体封装通过堆叠的多芯片结构允许高集成度和操作性能的提高。

公开(公告)号：US06713856B2

公开(公告)日：2004-03-30

申请号：US10232729

申请日：2002-09-03

申请人： Chung-Che Tsai ,  Wei-Heng Shan

发明人： Chung-Che Tsai ,  Wei-Heng Shan

IPC分类号： H01L2302

CPC分类号： H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A stacked chip package has a substrate with a through hole. A first chip is received in the through hole. A second chip is disposed on the first chip. Two chips are electrically connected to an upper surface of the substrate. An adhesive layer and a planar member, which are thermally and electrically conductive, are disposed on a lower surface of the substrate to support the chips and dissipate the heat generated by the chips. An encapsulant covers the upper surface of the substrate. The package has superior heat-dissipating ability, high yield in assembly and small size.

摘要翻译： 堆叠式芯片封装具有带有通孔的基板。 第一芯片被接收在通孔中。 第二芯片设置在第一芯片上。 两个芯片电连接到基板的上表面。 粘合剂层和平面构件是导热导电的，设置在基板的下表面上以支撑芯片并消散由芯片产生的热量。 密封剂覆盖基材的上表面。 该封装具有优异的散热能力，组装成品率高，体积小。