公开(公告)号：US06857865B2

公开(公告)日：2005-02-22

申请号：US10176145

申请日：2002-06-20

申请人： Chung-Che Tsai ,  Wei-Heng Shan

发明人： Chung-Che Tsai ,  Wei-Heng Shan

IPC分类号： B29C45/14 ,  B29C45/26 ,  B29C45/56 ,  H01L21/56

CPC分类号： H01L21/565 ,  B29C45/14655 ,  B29C45/14836 ,  B29C45/2602 ,  B29C45/56 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A mold structure for package fabrication is proposed, and includes a top mold, a fixture and a bottom mold. The top mold is formed with at least an upwardly recessed portion; the fixture is formed with a plurality of downwardly recessed portions; and the bottom mold has a recessed cavity for receiving the fixture therein, and adapted to be engaged with the top mold, wherein a resilient member is disposed on an inner wall of the recessed cavity, and interposed between the fixture and the recessed cavity of the bottom mold, allowing the resilient member to provide a resilient force for properly positioning the fixture. By using the above mold structure, chips mounted on a substrate can be firmly supported in the mold structure without causing chip cracks during a molding process for encapsulating the chips.

摘要翻译： 提出了一种用于封装制造的模具结构，包括顶模，夹具和底模。 顶模形成有至少一个向上凹入的部分; 夹具形成有多个向下凹陷部分; 并且底模具有用于在其中容纳固定件的凹腔，并且适于与顶模接合，其中弹性构件设置在凹腔的内壁上，并且插入在固定件与凹部的凹腔之间 底部模具，允许弹性构件提供用于适当地定位固定装置的弹性力。 通过使用上述模具结构，可以在模具结构中牢固地支撑安装在基板上的芯片，而不会在用于封装芯片的模制过程中引起芯片裂纹。

公开(公告)号：US06713856B2

公开(公告)日：2004-03-30

申请号：US10232729

申请日：2002-09-03

申请人： Chung-Che Tsai ,  Wei-Heng Shan

发明人： Chung-Che Tsai ,  Wei-Heng Shan

IPC分类号： H01L2302

CPC分类号： H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A stacked chip package has a substrate with a through hole. A first chip is received in the through hole. A second chip is disposed on the first chip. Two chips are electrically connected to an upper surface of the substrate. An adhesive layer and a planar member, which are thermally and electrically conductive, are disposed on a lower surface of the substrate to support the chips and dissipate the heat generated by the chips. An encapsulant covers the upper surface of the substrate. The package has superior heat-dissipating ability, high yield in assembly and small size.

摘要翻译： 堆叠式芯片封装具有带有通孔的基板。 第一芯片被接收在通孔中。 第二芯片设置在第一芯片上。 两个芯片电连接到基板的上表面。 粘合剂层和平面构件是导热导电的，设置在基板的下表面上以支撑芯片并消散由芯片产生的热量。 密封剂覆盖基材的上表面。 该封装具有优异的散热能力，组装成品率高，体积小。

公开(公告)号：US06911604B2

公开(公告)日：2005-06-28

申请号：US10210091

申请日：2002-08-02

申请人： Chung-Che Tsai ,  Wei-Heng Shan

发明人： Chung-Che Tsai ,  Wei-Heng Shan

IPC分类号： H01L23/498 ,  H05K3/24 ,  H05K3/34 ,  H05K1/03

CPC分类号： H05K3/3452 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K3/244 ,  H05K2201/09745 ,  H05K2201/09827 ,  H05K2201/099 ,  H05K2203/0594 ,  H01L2924/00

摘要： A printed circuit board, which comprises a substrate, a conductive pattern disposed on a surface of said substrate and a solder mask coated on the surface of said substrate and covered over the conductive pattern. The conductive pattern has a bonding pad. The solder mask has an opening corresponding in location to the bonding pad such that a portion of the bonding pad is exposed outside. A space is left between said solder mask and said bonding pad and is communicated with the opening. Whereby, a solder ball can be received in the opening and the space and electrically connected to the bonding pad, such that the solder ball is held on the printed circuit board securely.

摘要翻译： 一种印刷电路板，其包括基板，设置在所述基板的表面上的导电图案和涂覆在所述基板的表面上且覆盖在导电图案上的焊接掩模。 导电图案具有接合焊盘。 焊接掩模具有与焊盘的位置对应的开口，使得焊盘的一部分暴露在外部。 所述焊接掩模和所述接合焊盘之间留有空间，并与开口连通。 由此，可以在开口和空间中容纳焊球并电连接到焊盘，使得焊球牢固地保持在印刷电路板上。

公开(公告)号：US06709894B2

公开(公告)日：2004-03-23

申请号：US10170665

申请日：2002-06-12

申请人： Chung-Che Tsai ,  Wei-Heng Shan ,  Huan-Ping Su

发明人： Chung-Che Tsai ,  Wei-Heng Shan ,  Huan-Ping Su

IPC分类号： H01L2144

CPC分类号： H01L25/0652 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/97 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.

摘要翻译： 提供半导体封装及其制造方法。 多个第一芯片安装在基板上并电连接到基板。 包括屏蔽部分和支撑部分的屏蔽结构安装在基板上，其中支撑部分抵靠基板，并且屏蔽部分形成有与第一芯片相对应的多个开口。 通过开口施加粘合剂以在第一芯片上分别形成粘合剂层。 在从基板移除屏蔽结构之后，将多个第二芯片分别堆叠在粘合剂层上并电连接到基板。 通过进行成形和分割工艺，将封装结构单个化以形成单独的半导体封装。 以间歇形式形成粘合剂层的特征在于使制造成本和时间显着降低。

公开(公告)号：US06555919B1

公开(公告)日：2003-04-29

申请号：US10127918

申请日：2002-04-23

申请人： Chung-Che Tsai ,  Wei-Heng Shan

发明人： Chung-Che Tsai ,  Wei-Heng Shan

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/4899 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A low profile stack semiconductor package is proposed, wherein at least two chips having centrally-situated bond pads are stacked on a substrate that is formed with a through opening. A first chip is mounted on the substrate, with bond pads thereof being exposed to the opening. A second chip mounted on the first chip, is formed with a peripherally-situated cushion member, whereby bonding wires are adapted to extend from bond pads of the second chip in a direction parallel to the chip, and reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate, wherein the bonding wires are free of forming wire loops as extending above the second chip. By the above structure, the bonding wires would be firmly held in position to be free of contact or short circuit with the second chip, and overall package profile can be significantly miniaturized.

摘要翻译： 提出了一种薄型堆叠半导体封装，其中具有中心位置的焊盘的至少两个芯片堆叠在形成有通孔的衬底上。 第一芯片安装在基板上，其接合焊盘暴露于开口。 安装在第一芯片上的第二芯片形成有外围定位的缓冲构件，其中接合线适于沿着平行于芯片的方向从第二芯片的焊盘延伸，并到达缓冲构件，超过该衬垫 电线向下转动以指向基板，其中，接合线不会在第二芯片上方延伸形成线环。 通过上述结构，接合线将牢固地保持在与第二芯片无接触或短路的位置，并且整体封装轮廓可以显着地小型化。

公开(公告)号：US06849932B2

公开(公告)日：2005-02-01

申请号：US10232682

申请日：2002-09-03

申请人： Chung-Che Tsai ,  Wei-Heng Shan

发明人： Chung-Che Tsai ,  Wei-Heng Shan

IPC分类号： H01L23/29 ,  H01L23/31 ,  H01L23/36 ,  H01L23/433 ,  H01L23/498 ,  H01L25/065 ,  H01L23/495

CPC分类号： H01L23/4334 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49894 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention is to provide a double-sided thermally enhanced IC chip package which includes a chip being received in an opening of a substrate and electrically connected to a conductive circuit pattern on a top surface of the substrate through bonding wires. A thermally and electrically conductive planar member is attached to an inactive side of the chip through a thermally and electrically conductive adhesive layer. A portion of an active side of the chip to which the bonding wires are connected is encapsulated by a dielectric encapsulant, and the other portion of the active side of the chip is covered by a thermally and electrically conductive encapsulant. Thus, heat generated by the chip can be efficiently dissipated through the planar member and the thermally and electrically conductive encapsulant. The present invention also discloses a stacked chip package with double-sided heat dissipation capability.

摘要翻译： 本发明提供一种双面热增强IC芯片封装，其包括芯片，该芯片被接收在基板的开口中并且通过接合线电连接到基板的顶表面上的导电电路图案。 导电和导电的平面构件通过导热和导电的粘合剂层附着到芯片的非活动侧。 键合线连接的芯片的有效侧的一部分被介电密封剂封装，并且芯片的有源侧的另一部分由导电和导电的密封剂覆盖。 因此，可以通过平面构件和导热密封剂有效地散发由芯片产生的热量。 本发明还公开了具有双面散热能力的堆叠式芯片封装。

公开(公告)号：US06683385B2

公开(公告)日：2004-01-27

申请号：US10127983

申请日：2002-04-23

申请人： Chung-Che Tsai ,  Wei-Heng Shan

发明人： Chung-Che Tsai ,  Wei-Heng Shan

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A low profile stack semiconductor package is proposed. A lower chip having centrally-situated bond pads is mounted on a substrate, and electrically connected to the substrate by bonding wires. A cushion member is peripherally situated on the lower chip, allowing the bonding wires to extend from the bond pads in a direction parallel to the lower chip, and to reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate. An adhesive is applied on the lower chip, for encapsulating the bond pads, cushion member and bonding wires. This allows an upper chip to be readily stacked on the lower chip by attaching the upper chip to the adhesive, without affecting or damaging structural or electrical arrangement formed on the lower chip.

摘要翻译： 提出了一种薄型堆叠半导体封装。 具有中心位置的接合焊盘的下部芯片安装在基板上，并通过接合线电连接到基板。 缓冲构件周边地位于下芯片上，允许接合线在平行于下芯片的方向上从接合焊盘延伸，并且到达缓冲构件，接合线向下转动以朝向衬底。 在下芯片上施加粘合剂，用于封装接合垫，缓冲构件和接合线。 这允许通过将上部芯片附接到粘合剂而将上部芯片容易地堆叠在下部芯片上，而不会影响或损坏形成在下部芯片上的结构或电气布置。

公开(公告)号：US20050062152A1

公开(公告)日：2005-03-24

申请号：US10671176

申请日：2003-09-24

申请人： Chung-Che Tsai

发明人： Chung-Che Tsai

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L21/565 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A window ball grid array (WBGA) semiconductor package and a fabrication method thereof are provided. This WBGA package includes: a substrate having a through opening; a chip mounted on an upper surface and over the opening of the substrate via an adhesive, and electrically connected to a lower surface of the substrate via bonding wires through the opening, with gaps, not applied with the adhesive, formed between the chip and the substrate; a first encapsulation body made of a resin material for encapsulating the chip and the bonding wires, allowing the resin material to pass through the gaps to fill the opening of the substrate and the gaps; a second encapsulation body for covering the part of the first encapsulation body on the lower surface of the substrate; and a plurality of solder balls bonded to area free of the second encapsulation body on the lower surface of the substrate.

摘要翻译： 提供了一种窗户球栅阵列（WBGA）半导体封装及其制造方法。 该WBGA封装包括：具有通孔的衬底; 通过粘合剂安装在基板的上表面和开口上方的芯片，并且通过接合线通过开口电连接到衬底的下表面，其中间隙形成在芯片和芯片之间， 基质; 由用于封装芯片和接合线的树脂材料制成的第一封装体，允许树脂材料通过间隙以填充基板的开口和间隙; 第二封装体，用于覆盖所述基板的下表面上的所述第一封装体的所述部分; 以及在衬底的下表面上接合到没有第二包封体的区域的多个焊球。

公开(公告)号：US06849915B1

公开(公告)日：2005-02-01

申请号：US10649847

申请日：2003-08-26

申请人： Chung-Che Tsai

发明人： Chung-Che Tsai

IPC分类号： H01L21/00 ,  H01L31/0203 ,  H01L31/0232

CPC分类号： H01L31/0203 ,  H01L31/02325 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： A light sensitive semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a chip carrier and encompassed by a dam, and an infrared filter is attached to the dam to hermetically isolate the chip from the atmosphere. An encapsulant is formed on the chip carrier and surrounds the dam, and a lens is supported by the encapsulant to be positioned above the infrared filter. This allows light to penetrate through the infrared filter and lens to reach the chip. Before forming the encapsulant and mounting the lens, the semi-fabricated package with the chip being hermetically isolated by the infrared filter and dam is subject to a leak test, allowing a semi-fabricated package successfully passing the test to be formed with the encapsulant and lens, so as to reduce fabrication costs and improve yield of fabricated package products.

摘要翻译： 提供了一种光敏半导体封装及其制造方法，其中芯片安装在芯片载体上并被堤坝包围，并且红外滤光器附接到坝以将芯片与大气隔离。 密封剂形成在芯片载体上并围绕坝，并且透镜由密封剂支撑以定位在红外滤光器上方。 这允许光穿过红外滤光镜和透镜到达芯片。 在形成密封剂并安装透镜之前，具有通过红外滤光器和阻流器密封隔离的芯片的半制成封装进行泄漏测试，允许半制成封装成功地通过使用密封剂形成的测试， 透镜，以便降低制造成本并提高制造的包装产品的产量。

公开(公告)号：US06326700B1

公开(公告)日：2001-12-04

申请号：US09639202

申请日：2000-08-15

申请人： Jinchuan Bai ,  Chung-Che Tsai

发明人： Jinchuan Bai ,  Chung-Che Tsai

IPC分类号： H01L2329

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A low-profile semiconductor device is disclosed which includes a substrate having a base layer formed with at least a hole and a plurality of conductive traces arranged on the base layer. A semiconductor die is attached to the base layer of the substrate opposite to the conductive traces and electrically connected to the conductive traces by a plurality of first conductive elements passing through the hole of the base layer. A plurality of second conductive elements are arrayedly connected to the terminal of each of the conductive traces for providing externally electrical connection to the semiconductor die. The semiconductor die is encapsulated by a first encapsulant formed on the surface of the substrate on which the semiconductor die is mounted. A second encapsulant is formed on the surface of the substrate on which the conductive traces are arranged to completely encapsulate the conductive traces, first conductive elements and the hole. Meanwhile, the second encapsulant is formed to encapsulate the second conductive elements in such a manner that the bottom ends of the second conductive elements are exposed to and flush with the bottom surface of the second encapsulant.

摘要翻译： 公开了一种低轮廓半导体器件，其包括具有至少形成有孔的基底层和布置在基底层上的多个导电迹线的基板。 半导体管芯附着到与导电迹线相对的基板的基底层，并且通过穿过基底层的孔的多个第一导电元件电连接到导电迹线。 多个第二导电元件阵列地连接到每个导电迹线的端子，以提供与半导体管芯的外部电连接。 半导体管芯由形成在其上安装半导体管芯的衬底的表面上的第一密封剂封装。 第二密封剂形成在衬底的表面上，导电迹线布置在其上以完全封装导电迹线，第一导电元件和孔。 同时，形成第二密封剂以使第二导电元件的底端暴露于第二密封剂的底表面并与其平齐的方式封装第二导电元件。