公开(公告)号：US20170213907A1

公开(公告)日：2017-07-27

申请号：US15313448

申请日：2015-06-03

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Akitaka SOENO ,  Sachiko AOI ,  Shinichiro MIYAHARA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734

Abstract: High voltage-resistance of a switching device including a p-type region being in contact with a lower end of a bottom-insulating-layer is realized. The switching device includes a bottom-insulating-layer disposed at a bottom in a trench, and a gate electrode disposed on a front surface side of the bottom-insulating-layer. A semiconductor substrate includes a first n-type and p-type regions being in contact with the gate insulating film, a second p-type region being in contact with an end of the bottom-insulating-layer, and a second n-type region separating the second p-type region from the first p-type region. Distance A from a rear-surface-side-end of the first p-type region to a front-surface-side-end of the second p-type region, and distance B from a rear-surface-side-end of the-bottom-insulating layer to a rear-surface-side-end of the second p-type region satisfy A

公开(公告)号：US20170018643A1

公开(公告)日：2017-01-19

申请号：US15124326

申请日：2015-02-10

Applicant: Toyota Jidosha Kabushiki Kaisha ,  Denso Corporation

Inventor： Hidefumi TAKAYA ,  Jun SAITO ,  Akitaka SOENO ,  Toshimasa YAMAMOTO ,  Narumasa SOEJIMA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/761 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L21/761 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.

Abstract translation: 本文提供的半导体器件包括：p型的第四区域与栅极沟槽的下端接触; 在第二区域外的范围内设置在前表面的终端沟槽; p型的下端p型区域与端接沟槽的下端接触; p型侧面p型区域与外周侧的终端沟槽的侧面接触，与下端p型区域连接并露出在前表面上; 以及相对于侧面p型区域在外周侧设置并暴露在前表面上的多个保护环区域。

公开(公告)号：US20160247910A1

公开(公告)日：2016-08-25

申请号：US15025930

申请日：2014-09-15

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Naohiro SUZUKI ,  Sachiko AOI ,  Yukihiko WATANABE ,  Akitaka SOENO ,  Masaki KONISHI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/167

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer; a current dispersion layer; a base region; a source region; trenches; a gate insulation film; a gate electrode; a source electrode; a drain electrode; and a bottom layer. The current dispersion layer is arranged on the drift layer, and has a first conductive type with an impurity concentration higher than the drift layer. The bottom layer has a second conductive type, is arranged under the base region, covers a bottom of each trench including a corner portion of the bottom of the trench, and has a depth equal to or deeper than the current dispersion layer.

Abstract translation: 碳化硅半导体器件包括：衬底; 漂移层 电流色散层; 基地区 源区; 沟渠 栅极绝缘膜; 栅电极; 源电极; 漏电极; 和底层。 电流色散层布置在漂移层上，并且具有杂质浓度高于漂移层的第一导电类型。 底层具有第二导电类型，布置在基底区域下方，覆盖每个沟槽的底部，其包括沟槽底部的角部，并且具有等于或深于当前分散层的深度。

公开(公告)号：US20170084735A1

公开(公告)日：2017-03-23

申请号：US15365150

申请日：2016-11-30

Applicant: Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Naohiro SUZUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/417 ,  H01L29/872 ,  H01L29/15 ,  H01L21/761

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US20230125063A1

公开(公告)日：2023-04-20

申请号：US18065916

申请日：2022-12-14

Applicant: DENSO CORPORATION

Inventor： Seiji NOMA ,  Tomofusa SHIGA ,  Kouji SENDA ,  Tsuyoshi NISHIWAKI ,  Yuta FURUMURA ,  Akitaka SOENO

IPC: H01L29/47 ,  H01L27/06 ,  H01L29/739 ,  H01L29/872 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor substrate and a metal film. The metal film is located on the semiconductor substrate. The metal film includes a portion to have a Schottky junction with the semiconductor substrate. The metal film is made of an aluminum alloy in which an element is added to aluminum. The metal film includes a lower metal layer and an upper metal layer. The lower metal layer is located on the semiconductor substrate. The upper metal layer stacks on the lower metal layer. The lower metal layer has a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer.

公开(公告)号：US20140175508A1

公开(公告)日：2014-06-26

申请号：US14138456

申请日：2013-12-23

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Naohiro SUZUKI ,  Akitaka SOENO ,  Sachiko AOI ,  Yukihiko WATANABE

IPC: H01L29/872 ,  H01L29/739

CPC classification number: H01L29/872 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/7806 ,  H01L29/7813

Abstract: A semiconductor device includes a first conductivity-type drift region including an exposed portion, a plurality of second conductivity-type body regions, a first conductivity-type source region, a gate portion and a Schottky electrode. The drift region is defined in a semiconductor layer, and the exposed portion exposes on a surface of the semiconductor layer. The body regions are disposed on opposite sides of the exposed portion. The source region is separated from the drift region by the body region. The gate portion is disposed to oppose the body region. The exposed portion is formed with a groove, and the Schottky electrode is disposed in the groove. The Schottky electrode has a Schottky contact with the exposed portion.

Abstract translation: 半导体器件包括：第一导电型漂移区，包括暴露部分，多个第二导电型体区，第一导电型源区，栅极部和肖特基电极。 漂移区被限定在半导体层中，并且暴露部分暴露在半导体层的表面上。 主体区域设置在暴露部分的相对侧上。 源区域通过身体区域与漂移区域分离。 门部分设置成与身体区域相对。 暴露部分形成有凹槽，并且肖特基电极设置在凹槽中。 肖特基电极与暴露部分具有肖特基接触。

公开(公告)号：US20180212028A1

公开(公告)日：2018-07-26

申请号：US15878143

申请日：2018-01-23

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Takashi KUNO ,  Hiroki TSUMA ,  Satoshi KUWANO ,  Akitaka SOENO ,  Toshitaka KANEMARU ,  Kenta HASHIMOTO ,  Noriyuki KAKIMOTO ,  Shuji YONEDA

IPC: H01L29/417 ,  H01L23/31 ,  H01L23/00 ,  H01L21/285 ,  H01L29/45 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L29/41708 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/32133 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/53223 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L29/0696 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66348 ,  H01L29/7397 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05018 ,  H01L2224/05076 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05224 ,  H01L2224/05347 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01014

Abstract: A semiconductor device may include: a semiconductor substrate; a surface electrode covering a surface of the semiconductor substrate; an insulating protection film covering a part of a surface of the surface electrode; and a solder-bonding metal film, the solder-bonding metal film covering a range spreading from a surface of the insulating protection film to the surface of the surface electrode, wherein the surface electrode may include: a first metal film provided on the semiconductor substrate; a second metal film being in contact with a surface of the first metal film, and having tensile strength higher than tensile strength of the first metal film; and a third metal film being in contact with a surface of the second metal film, and having tensile strength which is lower than the tensile strength of the second metal film and is higher than the tensile strength of the first metal film.

公开(公告)号：US20150333127A1

公开(公告)日：2015-11-19

申请号：US14652483

申请日：2013-12-19

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Tomoo MORINO ,  Shoji MIZUNO ,  Yuichi TAKEUCHI ,  Akitaka SOENO ,  Yukihiko WATANABE

IPC: H01L29/16 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/761 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0642 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7815

Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.

Abstract translation: 碳化硅半导体器件包括：元件隔离层和电场弛豫层。 元件隔离层从基区的表面配置为比基区更深，位于主单元区域和感测单元区域之间，并且将主单元区域与感测单元区域隔离。 电场弛豫层从基底区域的底部排列成比元件隔离层更深。 电场弛豫层被分成主单元区域部分和感测单元区域部分。 元件隔离层的至少一部分布置在电场弛豫层的分割部分的内部。