公开(公告)号：US20060040103A1

公开(公告)日：2006-02-23

申请号：US11147670

申请日：2005-06-07

申请人： Jeffery Whiteford ,  Rhett Brewer ,  Mihai Buretea ,  Jian Chen ,  Karen Cruden ,  Xiangfeng Duan ,  William Freeman ,  David Heald ,  Francisco Leon ,  Chao Liu ,  Andreas Meisel ,  Kyu Min ,  J. Parce ,  Erik Scher

发明人： Jeffery Whiteford ,  Rhett Brewer ,  Mihai Buretea ,  Jian Chen ,  Karen Cruden ,  Xiangfeng Duan ,  William Freeman ,  David Heald ,  Francisco Leon ,  Chao Liu ,  Andreas Meisel ,  Kyu Min ,  J. Parce ,  Erik Scher

IPC分类号： B32B5/16

CPC分类号： C09C1/3081 ,  B82Y30/00 ,  C01P2004/16 ,  C01P2004/45 ,  C01P2004/54 ,  C01P2004/64 ,  C01P2006/10 ,  C01P2006/40 ,  C01P2006/60 ,  C09C3/006 ,  C09C3/063 ,  C09C3/12 ,  H01G4/14 ,  Y10S977/773 ,  Y10T428/2982 ,  Y10T428/2989 ,  Y10T428/2991 ,  Y10T428/2993 ,  Y10T428/2995 ,  Y10T428/2996 ,  Y10T428/2998

摘要： Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.

公开(公告)号：US20050287717A1

公开(公告)日：2005-12-29

申请号：US11148001

申请日：2005-06-07

申请人： David Heald ,  Karen Cruden ,  Xiangfeng Duan ,  Chao Liu ,  J. Parce

发明人： David Heald ,  Karen Cruden ,  Xiangfeng Duan ,  Chao Liu ,  J. Parce

IPC分类号： G03F7/075 ,  G11C13/00 ,  H01L21/28 ,  H01L21/312 ,  H01L21/469 ,  H01L21/82 ,  H01L27/10 ,  H01L29/739

CPC分类号： G03F7/0757 ,  B82Y10/00 ,  B82Y30/00 ,  G11C13/00 ,  H01L21/02137 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/28273 ,  H01L21/3124 ,  Y10S977/755 ,  Y10S977/845 ,  Y10S977/855 ,  Y10S977/936 ,  Y10S977/938

摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

摘要翻译： 提供了形成或构图纳米结构阵列的方法。 所述方法包括在包含纳米结构缔合基团的涂层上形成阵列，使用抗蚀剂进行图案化和/或使用便于阵列形成的装置。 还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。

公开(公告)号：US20080032134A1

公开(公告)日：2008-02-07

申请号：US11706730

申请日：2007-02-13

申请人： Jeffery Whiteford ,  Rhett Brewer ,  Mihai Buretea ,  Jian Chen ,  Karen Cruden ,  Xiangfeng Duan ,  William Freeman ,  David Heald ,  Francisco Leon ,  Chao Liu ,  Andreas Meisel ,  Kyu Min ,  J. Parce ,  Erik Scher

发明人： Jeffery Whiteford ,  Rhett Brewer ,  Mihai Buretea ,  Jian Chen ,  Karen Cruden ,  Xiangfeng Duan ,  William Freeman ,  David Heald ,  Francisco Leon ,  Chao Liu ,  Andreas Meisel ,  Kyu Min ,  J. Parce ,  Erik Scher

IPC分类号： B32B5/16 ,  B32B15/04 ,  B32B17/06

CPC分类号： C09C1/3081 ,  B82Y30/00 ,  C01P2004/16 ,  C01P2004/45 ,  C01P2004/54 ,  C01P2004/64 ,  C01P2006/10 ,  C01P2006/40 ,  C01P2006/60 ,  C09C3/006 ,  C09C3/063 ,  C09C3/12 ,  H01G4/14 ,  Y10S977/773 ,  Y10T428/2982 ,  Y10T428/2989 ,  Y10T428/2991 ,  Y10T428/2993 ,  Y10T428/2995 ,  Y10T428/2996 ,  Y10T428/2998

摘要： Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.

摘要翻译： 提供了用于制备离散涂层纳米结构的配体组合物，以及涂覆的纳米结构本身和结合其的装置。 还提供了在纳米结构上沉积后壳形成和用于可逆修饰纳米结构的方法。 本发明的配体和包被的纳米结构对于紧密堆积的纳米结构组合物是特别有用的，其可以改进纳米结构的量子限制和/或减少的串扰。

公开(公告)号：US20070032091A1

公开(公告)日：2007-02-08

申请号：US11495188

申请日：2006-07-28

申请人： David Heald ,  Karen Cruden ,  Xiangfeng Duan ,  Chao Liu ,  J. Parce

发明人： David Heald ,  Karen Cruden ,  Xiangfeng Duan ,  Chao Liu ,  J. Parce

IPC分类号： H01L21/31

CPC分类号： H01L21/28008 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/28229 ,  H01L21/28273 ,  H01L21/3105 ,  Y10S977/774 ,  Y10S977/782 ,  Y10S977/845 ,  Y10S977/855 ,  Y10S977/89 ,  Y10S977/891

摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

摘要翻译： 提供了形成或构图纳米结构阵列的方法。 所述方法包括在包含纳米结构缔合基团，自旋电介质中阵列形成，纳米结构沉积后的溶剂退火，使用抗蚀剂图案化和/或使用促进阵列形成的器件的涂层上形成阵列。 还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。

公开(公告)号：US20080150003A1

公开(公告)日：2008-06-26

申请号：US11641956

申请日：2006-12-20

申请人： Jian Chen ,  Xiangfeng Duan ,  Karen Cruden ,  Chao Liu ,  Madhuri L. Nallabolu ,  Srikanth Ranganathan ,  Francisco Leon ,  J. Wallace Parce

发明人： Jian Chen ,  Xiangfeng Duan ,  Karen Cruden ,  Chao Liu ,  Madhuri L. Nallabolu ,  Srikanth Ranganathan ,  Francisco Leon ,  J. Wallace Parce

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/517

摘要： Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.

摘要翻译： 描述诸如非易失性存储器件的电子设备的方法和装置。 存储器件包括多层控制电介质，例如双层或三层。 多层控制电介质包括高k电介质材料如氧化铝（Al 2 O 3），氧化铪（HfO 2）和/或铪铝氧化物的混合膜的组合。 多层控制电介质提供增强的特性，包括增加的电荷保留，增强的存储器编程/擦除窗口，改进的可靠性和稳定性，具有单或多（例如二，三或四位）操作的可行性。

公开(公告)号：US20080150004A1

公开(公告)日：2008-06-26

申请号：US11688087

申请日：2007-03-19

申请人： Jian Chen ,  Xiangfeng Duan ,  Karen Cruden ,  Chao Liu ,  Madhuri L. Nallabolu ,  Srikanth Ranganathan ,  Francisco Leon ,  J. Wallace Parce

发明人： Jian Chen ,  Xiangfeng Duan ,  Karen Cruden ,  Chao Liu ,  Madhuri L. Nallabolu ,  Srikanth Ranganathan ,  Francisco Leon ,  J. Wallace Parce

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L29/517 ,  H01L29/7881

摘要： Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.

公开(公告)号：US20080026532A1

公开(公告)日：2008-01-31

申请号：US11850127

申请日：2007-09-05

申请人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

发明人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

IPC分类号： H01L21/336

CPC分类号： H01L29/7887 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

公开(公告)号：US20070247904A1

公开(公告)日：2007-10-25

申请号：US11766980

申请日：2007-06-22

申请人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

发明人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

IPC分类号： G11C16/04

CPC分类号： H01L29/7887 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

公开(公告)号：US20050201149A1

公开(公告)日：2005-09-15

申请号：US11018572

申请日：2004-12-21

申请人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

发明人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/936 ,  Y10S977/943

摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

公开(公告)号：US20070187768A1

公开(公告)日：2007-08-16

申请号：US11695728

申请日：2007-04-03

申请人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

发明人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

IPC分类号： H01L29/94

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。