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    Artificial dielectrics using nanostructures
    9.
    发明授权
    Artificial dielectrics using nanostructures 失效
    使用纳米结构的人造电介质

    公开(公告)号：US07365395B2

    公开(公告)日：2008-04-29

    申请号：US11203432

    申请日：2005-08-15

    申请人： David P. Stumbo ,  Stephen A. Empedocles ,  Francisco Leon ,  J. Wallace Parce

    发明人： David P. Stumbo ,  Stephen A. Empedocles ,  Francisco Leon ,  J. Wallace Parce

    IPC分类号： H01L29/72

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  G11C2213/16 ,  G11C2213/81 ,  H01L29/0673 ,  H01L29/4908 ,  H01L51/0537 ,  Y10S977/743 ,  Y10S977/745 ,  Y10S977/762 ,  Y10S977/813 ,  Y10S977/936

    摘要： Artificial dielectrics using nanostructures, such as nanowires, are disclosed. In embodiments, artificial dielectrics using other nanostructures, such as nanorods, nanotubes or nanoribbons and the like are disclosed. The artificial dielectric includes a dielectric material with a plurality of nanowires (or other nanostructures) embedded within the dielectric material. Very high dielectric constants can be achieved with an artificial dielectric using nanostructures. The dielectric constant can be adjusted by varying the length, diameter, carrier density, shape, aspect ratio, orientation and density of the nanostructures. Additionally, a controllable artificial dielectric using nanostructures, such as nanowires, is disclosed in which the dielectric constant can be dynamically adjusted by applying an electric field to the controllable artificial dielectric. A wide range of electronic devices can use artificial dielectrics with nanostructures to improve performance. Example devices include, capacitors, thin film transistors, other types of thin film electronic devices, microstrip devices, surface acoustic wave (SAW) filters, other types of filters, and radar attenuating materials (RAM).

    摘要翻译： 公开了使用纳米结构的人造电介质，例如纳米线。 在实施例中，公开了使用其他纳米结构的人造电介质，例如纳米棒，纳米管或纳米带等。 人造电介质包括具有嵌入电介质材料内的多个纳米线（或其他纳米结构）的电介质材料。 使用纳米结构的人造电介质可以实现非常高的介电常数。 可以通过改变纳米结构的长度，直径，载流子密度，形状，纵横比，取向和密度来调节介电常数。 此外，公开了使用纳米结构的可控人造电介质，例如纳米线，其中可以通过向可控人造电介质施加电场来动态地调整介电常数。 各种电子器件可以使用具有纳米结构的人造电介质来提高性能。 示例性器件包括电容器，薄膜晶体管，其他类型的薄膜电子器件，微带器件，表面声波（SAW）滤波器，其它类型的滤波器以及雷达衰减材料（RAM）。

    Gate configuration for nanowire electronic devices
    10.
    发明授权
    Gate configuration for nanowire electronic devices 失效
    纳米线电子器件的栅极配置

    公开(公告)号：US07473943B2

    公开(公告)日：2009-01-06

    申请号：US11233398

    申请日：2005-09-22

    申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    IPC分类号： H01L29/80

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。