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公开(公告)号：US5586081A
公开(公告)日：1996-12-17
申请号：US447629
申请日：1995-05-23
申请人： Duane R. Mills , Richard Fackenthal , Rod Rozman , Mamun Rashid
发明人： Duane R. Mills , Richard Fackenthal , Rod Rozman , Mamun Rashid
CPC分类号： G11C8/18 , G06F12/0607 , G06F2212/2022
摘要： Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has a master latch to receive and store an external address. A first slave latch is also included to receive and store the external address from the master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.
摘要翻译： 描述了具有至少第一和第二组存储器阵列的存储器件的同步地址锁存电路。 锁存电路具有用于接收和存储外部地址的主锁存器。 如果外部地址属于第一个存储区，并且将外部地址作为第一个地址提供给第一个存储区，还包括一个第一从锁存器，用于从主存储器接收和存储外部地址。 如果外部地址属于第二组，则包括第二从锁存器以接收并存储来自主锁存器的外部地址，并将外部地址作为第二地址提供给第二存储体。
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公开(公告)号：US5497355A
公开(公告)日：1996-03-05
申请号：US253842
申请日：1994-06-03
申请人： Duane R. Mills , Richard Fackenthal , Rod Rozman , Mamun Rashid
发明人： Duane R. Mills , Richard Fackenthal , Rod Rozman , Mamun Rashid
CPC分类号： G11C8/18 , G06F12/0607 , G06F2212/2022
摘要： Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has first and second master latches to receive and store an external address. A first slave latch is also included to receive and store the external address from the first master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the second master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.
摘要翻译： 描述了具有至少第一和第二组存储器阵列的存储器件的同步地址锁存电路。 锁存电路具有用于接收和存储外部地址的第一和第二主锁存器。 如果外部地址属于第一个存储区并且将外部地址作为第一个地址提供给第一个存储体，则还包括一个第一从锁存器，用于从第一主锁存器接收和存储外部地址。 如果外部地址属于第二组，并且将外部地址作为第二地址提供给第二组，则包括第二从锁存器以从第二主锁存器接收和存储外部地址。
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公开(公告)号：US5410544A
公开(公告)日：1995-04-25
申请号：US085641
申请日：1993-06-30
CPC分类号： G11C29/48
摘要： An apparatus for testing a unit comprising an internal processor coupled to a register by an internal bus. The internal processor is programmed so that it can execute an algorithm. When executed, the algorithm performs an operation on the unit. The register is for storing a state datum. The internal bus is used by the internal processor to access the state datum when the internal processor is executing the algorithm. The testing apparatus comprises an external processor disposed external to the unit and an interface and switch disposed on the unit. The interface is coupled to the internal and external processors and is for receiving a plurality of commands from the external processor. The commands include an internal processor command and an open trap command. If issued, the internal processor command causes the internal processor to execute the algorithm. The switch is coupled to the interface and coupled between the internal processor and the internal bus. If the interface receives the open trap command, the switch permits the external processor to access the state datum of the register.
摘要翻译： 一种用于测试单元的装置，包括通过内部总线耦合到寄存器的内部处理器。 内部处理器被编程为可以执行一个算法。 执行时，算法对单元执行操作。 寄存器用于存储状态数据。 当内部处理器执行算法时，内部总线由内部处理器使用来访问状态数据。 测试装置包括设置在该单元外部的外部处理器和设置在该单元上的接口和开关。 该接口耦合到内部和外部处理器，并用于从外部处理器接收多个命令。 这些命令包括内部处理器命令和打开的陷阱命令。 如果发出内部处理器命令，内部处理器将执行该算法。 该开关耦合到接口并耦合在内部处理器和内部总线之间。 如果接口接收到打开的trap命令，则交换机允许外部处理器访问寄存器的状态数据。
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公开(公告)号：US20090316460A1
公开(公告)日：2009-12-24
申请号：US12141873
申请日：2008-06-18
CPC分类号： G11C29/4401 , G11C29/76 , G11C29/846 , G11C2029/0409
摘要： An apparatus for redundancy of a memory array includes a primary memory array including a plurality of memory cells, one or more of which are defective. A redundant array includes a CAM array that includes a plurality of memory cells. The CAM array is addressed by the address of a defective memory location within the primary memory array and provides a match identification and a resource identification. The redundant array also includes a translation array wherein an offset to configure an input/output multiplexer is stored. The redundant array also includes a redundant data array including a plurality of memory cells wherein one or more memory cells of the redundant data array are used instead of one or more defective memory cells of the primary array.
摘要翻译： 存储器阵列的冗余设备包括主存储器阵列，其包括多个存储器单元，其中一个或多个是有缺陷的。 冗余阵列包括包括多个存储单元的CAM阵列。 CAM阵列由主存储器阵列内的缺陷存储器位置的地址寻址，并提供匹配标识和资源标识。 冗余阵列还包括平移阵列，其中存储用于配置输入/输出多路复用器的偏移。 冗余阵列还包括冗余数据阵列，其包括多个存储器单元，其中使用冗余数据阵列的一个或多个存储器单元来代替主阵列的一个或多个缺陷存储器单元。
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公开(公告)号：US20050285642A1
公开(公告)日：2005-12-29
申请号：US10880983
申请日：2004-06-29
申请人： Mamun Rashid
发明人： Mamun Rashid
CPC分类号： H03L7/0814 , H04L25/0272 , H04L25/028
摘要： A device includes a number of output circuits to drive a number of output signals. The output signals have timing relationship among each other. The device also includes a control loop circuit serving as a feedback loop to adjust any mismatch between the timing relationships of the output signals.
摘要翻译： 一种装置包括多个输出电路来驱动多个输出信号。 输出信号之间具有定时关系。 该装置还包括用作反馈回路的控制回路电路，以调整输出信号的定时关系之间的任何失配。
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6.发明授权
公开(公告)号：US5623620A
公开(公告)日：1997-04-22
申请号：US85542
申请日：1993-06-30
CPC分类号： G11C29/48 , G01R31/318516 , G06F12/0246 , G11C11/005 , G11C16/10 , G11C29/26 , G06F11/2273 , G06F2212/7203
摘要： A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
摘要翻译： 一种具有特殊测试模式的页面缓冲电路的闪存设备。 页面缓冲电路包括平面A和平面B，每个平面包括静态随机存取存储器阵列。 页面缓冲电路还包括模式控制电路，其将平面A和平面B映射为可通过主机总线访问的连续扩展存储器空间。 页面缓冲电路还将平面A和平面B映射为闪存器件的闪存阵列控制器的控制存储器。
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公开(公告)号：US07684267B2
公开(公告)日：2010-03-23
申请号：US12141873
申请日：2008-06-18
IPC分类号： G11C7/00
CPC分类号： G11C29/4401 , G11C29/76 , G11C29/846 , G11C2029/0409
摘要： An apparatus for redundancy of a memory array includes a primary memory array including a plurality of memory cells, one or more of which are defective. A redundant array includes a CAM array that includes a plurality of memory cells. The CAM array is addressed by the address of a defective memory location within the primary memory array and provides a match identification and a resource identification. The redundant array also includes a translation array wherein an offset to configure an input/output multiplexer is stored. The redundant array also includes a redundant data array including a plurality of memory cells wherein one or more memory cells of the redundant data array are used instead of one or more defective memory cells of the primary array.
摘要翻译： 存储器阵列的冗余设备包括主存储器阵列，其包括多个存储器单元，其中一个或多个是有缺陷的。 冗余阵列包括包括多个存储单元的CAM阵列。 CAM阵列由主存储器阵列内的缺陷存储器位置的地址寻址，并提供匹配标识和资源标识。 冗余阵列还包括平移阵列，其中存储用于配置输入/输出多路复用器的偏移。 冗余阵列还包括冗余数据阵列，其包括多个存储器单元，其中使用冗余数据阵列的一个或多个存储器单元来代替主阵列的一个或多个缺陷存储器单元。
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公开(公告)号：US20070146035A1
公开(公告)日：2007-06-28
申请号：US11319689
申请日：2005-12-28
申请人： Hon-Mo Law , Mamun Rashid , Aaron Martin
发明人： Hon-Mo Law , Mamun Rashid , Aaron Martin
IPC分类号： H03K5/13
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0814 , H04L7/0337
摘要： An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations.
摘要翻译： 集成电路包括时钟偏移电路。 该偏斜电路包括多个回路电路，以使接收的时钟与数据眼对齐，并且减少由电压和温度变化引起的时钟漂移的影响。
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公开(公告)号：US20070006011A1
公开(公告)日：2007-01-04
申请号：US11172149
申请日：2005-06-30
申请人： Aaron Martin , Hing To , Mamun Rashid , Joe Salmon
发明人： Aaron Martin , Hing To , Mamun Rashid , Joe Salmon
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F13/40 , G06F13/4243 , G11C7/1033
摘要： De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.
摘要翻译： 以半字节为单位执行去偏移，其中半字节不限于四位。
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公开(公告)号：US20050140416A1
公开(公告)日：2005-06-30
申请号：US10746105
申请日：2003-12-24
申请人： Mamun Rashid
发明人： Mamun Rashid
CPC分类号： H03L7/0812 , H03K5/133 , H03K5/135 , H03K2005/00052 , H03K2005/00058 , H03L7/0805
摘要： Embodiments of the invention provide for a DLL architecture including a coarse-fine type arrangement using one loop for non-continuous strobe that can be also be adapted for continuous clocks as well. In particular, a reference loop establishes precise coarse unit delay. A slave delay line duplicates unit delay. A phase interpolator interpolates between unit delay to produce fine delay.
摘要翻译： 本发明的实施例提供了一种DLL架构，其包括使用用于非连续选通的一个循环的粗细型布置，该循环也可以适用于连续时钟。 特别地，参考循环建立精确的粗略单位延迟。 从属延迟线重复单位延迟。 相位插值器在单位延迟之间插值以产生精细延迟。
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