公开(公告)号：US09692408B2

公开(公告)日：2017-06-27

申请号：US14654127

申请日：2013-12-12

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Greg P. Klowak

IPC: H03K3/00 ,  H03K17/687 ,  H01L25/18 ,  H01L23/495 ,  H01F19/08 ,  H01L23/64 ,  H01L23/00

CPC classification number: H03K17/687 ,  H01F19/08 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12035 ,  H01L2924/1204 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic switching system and device comprising driver circuits for power transistors are disclosed, with particular application for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement, to a high voltage GaN HEMT and provides for improved control of noise and voltage transients. Monitoring and control functions, including latching and clamping, are based on monitoring of Vcc conditions for shut-down and start-up conditioning to enable safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

公开(公告)号：US09660639B2

公开(公告)日：2017-05-23

申请号：US15091867

申请日：2016-04-06

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Ahmad Mizan

IPC: H03K3/00 ,  H03K17/16 ,  H03K17/687 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417

CPC classification number: H03K17/162 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H03K17/168 ,  H03K17/6877

Abstract: Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

公开(公告)号：US09818692B2

公开(公告)日：2017-11-14

申请号：US15078023

申请日：2016-03-23

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Greg P. Klowak ,  Cameron McKnight-MacNeil

IPC: H01L23/528 ,  H01L21/66 ,  H01L27/095 ,  H01L29/40 ,  H01L29/778 ,  H01L23/373 ,  H01L29/20 ,  H01L29/06 ,  H01L23/36

CPC classification number: H01L23/528 ,  H01L22/32 ,  H01L23/36 ,  H01L23/3737 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

Abstract: Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.

公开(公告)号：US09105560B2

公开(公告)日：2015-08-11

申请号：US14105569

申请日：2013-12-13

Applicant: GAN SYSTEMS INC.

Inventor： John Roberts ,  Greg Klowak

IPC: H01L25/18 ,  H01L23/495 ,  H01F19/08 ,  H01L23/64 ,  H01L23/00

CPC classification number: H03K17/687 ,  H01F19/08 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12035 ,  H01L2924/1204 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Devices and systems comprising driver circuits are disclosed for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement to a high voltage GaN HEMT, for improved control of noise and voltage transients. Co-packaging of a GaN transistor die and a CMOS driver die using island topology contacts, through substrate vias, and a flip-chip, stacked configuration provides interconnections with low inductance and resistance, and provides effective thermal management. Co-packaging of a CMOS input interface circuit with the CMOS driver and GaN transistor allows for a compact, integrated CMOS driver with enhanced functionality including shut-down and start-up conditioning for safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

Abstract translation: 公开了包括驱动电路的器件和系统，用于MOSFET驱动的常规氮化镓（GaN）功率晶体管。 优选地，具有集成的低电压横向MOSFET驱动器的低功率高速CMOS驱动器电路以混合共源共栅布置串联耦合到高电压GaN HEMT，用于改善噪声和电压瞬变的控制。 使用岛拓扑触点，通过衬底通孔和倒装芯片堆叠配置来共同封装GaN晶体管管芯和CMOS驱动器管芯，提供低电感和电阻的互连，并提供有效的热管理。 CMOS输入接口电路与CMOS驱动器和GaN晶体管的共同封装允许具有增强功能的紧凑集成CMOS驱动器，包括关闭和启动调节，以实现更安全的操作，特别是对于高电压和高电流切换。 优选实施例还提供具有减小的输入损耗的隔离，自供电的高速驱动器件。

公开(公告)号：US10290623B2

公开(公告)日：2019-05-14

申请号：US15131309

申请日：2016-04-18

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Hugues Lafontaine

IPC: H01L27/02

Abstract: An integrated gate protection device P for a GaN power transistor D1 provides negative ESD spike protection. Protection device P comprises a smaller gate width wg enhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D1, and the source of Pm is connected to the intrinsic source of D1. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors P1 to Pn, connected in series, it turns on when the gate input voltage applied to the drain of P1 goes negative by more than the sum of the threshold voltages of P1 to Pn. The combined gate width of P1 to Pn is selected to limit the gate voltage excursion of D1.

公开(公告)号：US09659854B2

公开(公告)日：2017-05-23

申请号：US15027012

申请日：2015-04-15

Applicant: GaN Systems Inc.

Inventor： Greg P. Klowak ,  Ahmad Mizan ,  John Roberts

IPC: H01L29/66 ,  H01L29/15 ,  H01L31/02 ,  H01L29/78 ,  H01L23/498 ,  H01L23/482 ,  H01L29/20 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L29/778

CPC classification number: H01L23/49844 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/19 ,  H01L24/20 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/78 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/82

Abstract: Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.

公开(公告)号：US09525413B2

公开(公告)日：2016-12-20

申请号：US15099459

申请日：2016-04-14

Applicant: GaN Systems Inc.

Inventor： John Roberts ,  Iain H. Scott

IPC: H03K3/00 ,  H03K17/687 ,  H01L29/778 ,  H01L29/20 ,  H03K5/08

CPC classification number: H03K17/687 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/7787 ,  H03K5/08 ,  H03K17/04123 ,  H03K2217/0036

Abstract: Driver circuitry for switching systems comprising enhancement mode (E-Mode) GaN power transistors with low threshold voltage is disclosed. An E-Mode high electron mobility transistor (HEMT) D3 has a monolithically integrated GaN driver, comprising smaller E-Mode GaN HEMTs D1 and D2, and a discrete dual-voltage pre-driver. In operation, D1 provides the gate drive voltage to the gate of the GaN switch D3, and D2 clamps the gate of the GaN switch D3 to the source, via an internal source-sense connection closely coupling the source of D3 and the source of D2. An additional source-sense connection is provided for the pre-driver. Boosting the drive voltage to the gate of D1 produces firm and rapid pull-up of D1 and D3 for improved switching performance at higher switching speeds. High current handling components of the driver circuitry are integrated with the GaN switch and closely coupled to reduce inductance, while the discrete pre-driver can be thermally separated from the GaN chip.

Abstract translation: 公开了包括具有低阈值电压的增强模式（E模式）GaN功率晶体管的开关系统的驱动电路。 E模式高电子迁移率晶体管（HEMT）D3具有单片集成的GaN驱动器，其包括更小的E型GaN HEMT D1和D2以及分立的双电压预驱动器。 在操作中，D1将栅极驱动电压提供给GaN开关D3的栅极，并且D2通过紧密耦合D3源和D2源的内部源极检测连接将GaN开关D3的栅极钳位到源极 。 为前置驱动程序提供了额外的源感测连接。 将D1和D3的驱动电压提升到D1的栅极，可以实现更快速的D1和D3上拉，从而提高开关速度下的开关性能。 驱动器电路的大电流处理部件与GaN开关集成，并且紧密耦合以减小电感，而离散预驱动器可以与GaN芯片热分离。