公开(公告)号：US09535319B2

公开(公告)日：2017-01-03

申请号：US14674157

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Paul Ackmann ,  Chin Teong Lim

IPC: G03F1/36 ,  G03F7/30 ,  H01L21/768

CPC classification number: G03F1/36

Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

Abstract translation: 一种方法包括提供至少一个掩模版的至少一部分的光学前邻近校正（OPC）布局。 预OPC布局定义了包括具有多个具有第一间距的第一目标特征的第一测试单元区域和具有多个具有第二间距的第二目标特征的第二测试单元区域的测试单元。 基于OPC前的布局形成了掩模版部分的后OPC布局。 后OPC布局的形成包括执行基于规则的OPC处理，其中，基于多个第一目标特征提供用于第一测试单元区域的多个第一掩模版特征，并且执行基于模型的OPC 处理，其中，基于所述多个第二目标特征提供用于所述第二测试单元区域的多个第二掩模版特征。

公开(公告)号：US09384318B2

公开(公告)日：2016-07-05

申请号：US14263340

申请日：2014-04-28

Applicant: Globalfoundries Inc.

Inventor： Guoxiang Ning ,  Paul Ackmann ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441

Abstract: Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio.

Abstract translation: 公开了用于使OPC模型能够解决掩模中的错误的方法和装置。 实施例包括：确定电路设计的图形层; 估计在制造的电路中指示用于形成图案化层的制造掩模的掩模角舍入误差的穿透比; 以及基于所述穿透比，由处理器确定所述电路设计的光学邻近校正的补偿度量。

公开(公告)号：US08895211B2

公开(公告)日：2014-11-25

申请号：US13710498

申请日：2012-12-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guoxiang Ning ,  Chunyu Wong ,  Paul Ackmann ,  Sarasvathi Thangaraju

IPC: G03F1/26

CPC classification number: G03F7/20 ,  G03F1/28 ,  G03F1/42 ,  G03F1/50

Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.

Abstract translation: 公开了一种掩模，其包括设置在掩模的第一侧上的多个第一相移区域和设置在掩模的第二侧上的多个第二相移区域。 第一相移区域和第二相移区域可以是交变相移区域，其中第一相移区域的相移与第二相移区域的相移相异，例如180度。 还公开了一种形成掩模的方法和使用该掩模的半导体器件制造方法。

公开(公告)号：US10002827B2

公开(公告)日：2018-06-19

申请号：US15458140

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Yuping Ren ,  Chin Teong Lim ,  Xusheng Wu ,  Paul Ackmann

IPC: G06F17/50 ,  H01L23/522 ,  G03F1/36 ,  H01L23/528

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US09368453B2

公开(公告)日：2016-06-14

申请号：US14948476

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Chan Seob Cho ,  Paul Ackmann ,  Jung Yu Hsieh ,  Hui Peng Koh

IPC: H01L23/544 ,  H01L29/49

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/3212 ,  H01L22/12 ,  H01L27/088 ,  H01L29/4916 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.

Abstract translation: 提供了基于覆盖标记的形状和所得到的装置在有源层区域上形成虚拟结构和覆盖标记保护区域的方法。 实施例包括确定重叠标记的尺寸和形状; 基于覆盖标记的形状确定覆盖标记保护区的大小和形状; 基于重叠标记的形状确定多个虚拟结构的形状; 基于覆盖标记和多个虚拟结构的尺寸和形状来确定活动层区域的尺寸和形状; 在半导体衬底的有源层中形成有源层区; 在所述半导体衬底的多晶硅层中的所述有源层区域上形成所述覆盖标记和所述多个虚设结构; 并平坦化多层。

公开(公告)号：US09250538B2

公开(公告)日：2016-02-02

申请号：US14146771

申请日：2014-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Christopher Spence ,  Paul Ackmann ,  Chin Teong Lim

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/70

CPC classification number: G03F7/70441 ,  G03F1/70 ,  Y02T10/82

Abstract: A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.

Abstract translation: 公开了一种用于高效光学邻近校正（OPC）修复流程的方法和装置。 实施例可以包括接收集成电路（IC）设计布局的输入数据流，对输入数据流执行OPC步骤的一个或多个迭代和布局抛光步骤，以及如果最后一个输出的输出执行智能增强步骤 OPC步骤的迭代不能满足一个或多个布局标准，并且如果一个或多个迭代的数量满足阈值。 附加实施例可以包括执行与OPC步骤交联的模式插入过程，模式插入过程是基本光学规则检查（ORC）过程。

公开(公告)号：US10923388B2

公开(公告)日：2021-02-16

申请号：US16252114

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Yuping Ren ,  Paul Ackmann ,  Guoxiang Ning

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/283 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

公开(公告)号：US09672312B2

公开(公告)日：2017-06-06

申请号：US14703179

申请日：2015-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

公开(公告)号：US09645486B2

公开(公告)日：2017-05-09

申请号：US14560388

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chin Teong Lim ,  Guoxiang Ning ,  Paul Ackmann

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F1/36

Abstract: Methods of calibrating an OPC model using converged results of CD measurements from at least two locations along a substrate profile of a 1D, 2D, or critical area structure are provided. Embodiments include calibrating an OPC model for a structure to be formed in a substrate; simulating a CD of the structure at at least two locations along a substrate profile of the structure using the OPC model; comparing the simulated CD of the structure at each location against a corresponding measured CD; recalibrating the OPC model based on the comparing of each simulated CD against the corresponding measured CD; repeating the steps of simulating, comparing, and recalibrating until comparing at a first of the at least two locations converges to a first criteria and comparing at each other of the at least two locations converges to a corresponding criteria; and forming the structure using the recalibrated OPC model.

公开(公告)号：US09323882B2

公开(公告)日：2016-04-26

申请号：US14228611

申请日：2014-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Guido Ueberreiter ,  Lloyd C. Litt ,  Paul Ackmann

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract translation: 提供了一种用于电路结构的度量图案布局，包括多个象限的计量图案布局，其中可以将象限第一晶片测量图案，第二晶片测量图案，标线片配准图案和掩模版测量图案布置成 有助于光栅测量数据与晶圆计量数据的相关性。 标线片配准图案还可以包括被设计成保护掩模版测量图案内的其它结构元件的一个或多个最外面的结构元件在光学邻近校正过程中被修改。 提供了一种光学邻近校正处理方法，其中可以获得分划板测量图案并将其分类以添加或修改光学邻近校正处理的规则集。