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    Rebalancing in twin cell memory schemes to enable multiple writes
    2.
    发明授权
    Rebalancing in twin cell memory schemes to enable multiple writes 有权
    重新平衡双胞细胞存储器方案以启用多次写入

    公开(公告)号：US09418745B1

    公开(公告)日：2016-08-16

    申请号：US14661383

    申请日：2015-03-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xiang Chen ,  Toshiaki Kirihata ,  Derek H. Leu ,  Dan Moy

    IPC: G11C16/04 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26

    CPC classification number: G11C16/14 ,  G11C16/10 ,  G11C16/20 ,  G11C16/26

    Abstract: A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.

    Abstract translation: 一种操作双晶体管，多时间可编程存储器（MTPM）存储单元的系统和方法，其确保在每个写周期之后读取的位值的精确再现性。 每个多时间可编程存储器单元包括第一晶体管和第二晶体管的串联连接。 该方法包括将选择存储单元位置处的写入电路写入到一个或多个选择存储单元的初始位值。 然后，使用写入电路，执行在每个选择存储单元处与一个或多个第一晶体管或第二晶体管相关联的参数的状态的再平衡。 然后，在每个重新平衡选择存储单元处执行擦除周期，写入的初始位值。 在一个实施例中，可以在重新平衡之前首先执行擦除循环。 在每个位值写周期之前执行重新平衡和擦除。

    Precision trench capacitor
    3.
    发明授权
    Precision trench capacitor 有权
    精密沟槽电容器

    公开(公告)号：US09240406B2

    公开(公告)日：2016-01-19

    申请号：US14257143

    申请日：2014-04-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kai D. Feng ,  Dan Moy ,  Chengwen Pei ,  Robert R. Robison ,  Pinping Sun ,  Richard A. Wachnik ,  Ping-Chuan Wang

    IPC: H01L27/07 ,  H01L29/66 ,  H01L29/94

    CPC classification number: H01L27/0733 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11206 ,  H01L29/66181 ,  H01L29/945

    Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

    Abstract translation: 电容器结构可以包括多个沟槽电容器的并联连接。 电连接多个沟槽电容器的第一节点以提供电容器结构的第一节点。 多个沟槽电容器的第二节点通过电容器结构的第二节点处的至少一个可编程电连接电连接在一起。 每个可编程电气连接可以包括可编程电熔丝和场效应晶体管中的至少一个，并且可以临时或永久地断开相应的沟槽电容器。 可以通过暂时或永久地编程至少一个可编程电连接来调节电容器结构的总电容。

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