公开(公告)号：US10236350B2

公开(公告)日：2019-03-19

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/768

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

公开(公告)号：US10181420B2

公开(公告)日：2019-01-15

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Michael Permana ,  Guillaume Bouche ,  Andy Wei ,  Mark Zaleski ,  Anbu Selvam K M Mahalingam ,  Craig Michael Child, Jr. ,  Roderick Alan Augur ,  Shyam Pal ,  Linus Jang ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20170263715A1

公开(公告)日：2017-09-14

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/49 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0273 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.