公开(公告)号：US09390979B2

公开(公告)日：2016-07-12

申请号：US14482529

申请日：2014-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Huy M. Cao ,  Jing Wan

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823437 ,  H01L27/088

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer.

Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成一组掩模。 这组掩模中的每个掩模覆盖至少一个源/漏（s / d）接触位置。 从半导体结构的未被该组掩模覆盖的其余部分去除氧化物层。 然后在除去氧化物层的剩余部分中形成相对掩模填充层。 然后从半导体结构的其余部分去除氧化物层，即，先前被该组掩模和触点覆盖的部分形成在通过去除其余部分形成的凹部中的至少s / d接触位置 氧化层。

公开(公告)号：US09455204B1

公开(公告)日：2016-09-27

申请号：US14727143

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy M. Cao ,  Jinping Liu ,  Guillaume Bouche ,  Huang Liu

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method of introducing N/P dopants in PMOS and NMOS fins at the SSRW layer without complicated processing and the resulting device are provided. Embodiments include forming a plurality of p-type and n-type fins on a substrate, the plurality of p-type and n-type fins formed with an ISSG or pad oxide layer; performing an n-well implant into the substrate through the ISSG or pad oxide layer; performing a first SRPD on the ISSG or pad oxide layer of the plurality of p-type fins; performing a p-well implant into the substrate through the ISSG or pad oxide layer; performing a second SRPD on the ISSG or pad oxide layer of the plurality of n-type fins; and driving the n-well and p-well implants and the SRPD dopants into a portion of the plurality of p-type and n-type fins.

Abstract translation: 在SSRW层的PMOS和NMOS鳍片中引入N / P掺杂剂而不需要复杂的处理并提供所得到的器件的方法。 实施例包括在基板上形成多个p型和n型翅片，多个p型和n型翅片形成有ISSG或衬垫氧化物层; 通过ISSG或衬垫氧化物层将n阱注入到衬底中; 在多个p型翅片的ISSG或衬垫氧化物层上执行第一SRPD; 通过ISSG或垫氧化物层进行p阱注入到衬底中; 在所述多个n型鳍片的ISSG或衬垫氧化物层上执行第二SRPD; 并且将n阱和p阱注入和SRPD掺杂剂驱动到多个p型和n型鳍中的一部分中。

公开(公告)号：US09589829B1

公开(公告)日：2017-03-07

申请号：US14982872

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy M. Cao ,  Daniel Jaeger ,  Guillaume Bouche

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of fins on a semiconductor substrate by defining a plurality of trenches in the substrate. A first insulating material layer comprising silicon, oxygen and carbon is formed in the trenches between the plurality of fins. The first insulating material layer has an upper surface that is at a level that is below an upper surface of the fins. A second insulating material layer is formed above the first insulating material layer. The second insulating material layer is planarized to expose a top surface of the plurality of fins. The second insulating material layer is removed to expose the first insulating material layer.

Abstract translation: 一种方法包括通过在衬底中限定多个沟槽，在半导体衬底上形成多个翅片。 在多个翅片之间的沟槽中形成包括硅，氧和碳的第一绝缘材料层。 第一绝缘材料层的上表面位于翅片上表面的下方。 第二绝缘材料层形成在第一绝缘材料层的上方。 第二绝缘材料层被平坦化以暴露多个翅片的顶表面。 去除第二绝缘材料层以露出第一绝缘材料层。

公开(公告)号：US10056458B2

公开(公告)日：2018-08-21

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho Maeng ,  Andy Wei ,  Anthony Ozzello ,  Bharat Krishnan ,  Guillaume Bouche ,  Haifeng Sheng ,  Haigou Huang ,  Huang Liu ,  Huy M. Cao ,  Ja-Hyung Han ,  SangWoo Lim ,  Kenneth A. Bates ,  Shyam Pal ,  Xintuo Dai ,  Jinping Liu

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.