公开(公告)号：US09293189B2

公开(公告)日：2016-03-22

申请号：US14549117

申请日：2014-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Torsten Klick

IPC: H01L21/331 ,  G11C11/4091 ,  G11C11/412 ,  H01L27/11 ,  H01L27/02

CPC classification number: G11C11/4091 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1104

Abstract: Integrated circuits that include SRAM cells having additional read stacks are provided. In accordance with one embodiment an integrated circuit includes a memory storage array of memory cells. The integrated circuit includes a read stack coupled to each memory cell of the memory storage array. Each read stack includes a read pull-down transistor having a first threshold voltage, and a read pass gate transistor coupled in series with the read pull down transistor and having a second threshold voltage greater than the first threshold voltage.

Abstract translation: 提供了包括具有附加读取堆栈的SRAM单元的集成电路。 根据一个实施例，集成电路包括存储器单元的存储器存储阵列。 集成电路包括耦合到存储器存储阵列的每个存储单元的读取堆栈。 每个读取堆叠包括具有第一阈值电压的读取下拉晶体管和与读出的下拉晶体管串联耦合并且具有大于第一阈值电压的第二阈值电压的读取通道栅极晶体管。

公开(公告)号：US20160247811A1

公开(公告)日：2016-08-25

申请号：US15146201

申请日：2016-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Igor Lusetsky ,  Ralf van Bentum

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11546 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal.

公开(公告)号：US09293556B2

公开(公告)日：2016-03-22

申请号：US14445893

申请日：2014-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L21/00 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.

Abstract translation: 本文所述的说明性半导体结构包括包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域的衬底。 逻辑晶体管设置在逻辑晶体管区域。 逻辑晶体管包括栅极电介质和栅电极。 输入/输出晶体管设置在输入/输出晶体管区域。 输入/输出晶体管包括栅极电介质和栅电极。 输入/输出晶体管的栅极电介质具有比逻辑晶体管的栅极电介质更大的厚度。 铁电晶体管设置在铁电晶体管区域。 铁电晶体管包括铁电电介质和栅电极。 铁电电介质布置在铁电晶体管区域和铁电晶体管的栅电极之间。

公开(公告)号：US20150078068A1

公开(公告)日：2015-03-19

申请号：US14549117

申请日：2014-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Torsten Klick

IPC: G11C11/4091

CPC classification number: G11C11/4091 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1104

Abstract: Integrated circuits that include SRAM cells having additional read stacks are provided. In accordance with one embodiment an integrated circuit includes a memory storage array of memory cells. The integrated circuit includes a read stack coupled to each memory cell of the memory storage array. Each read stack includes a read pull-down transistor having a first threshold voltage, and a read pass gate transistor coupled in series with the read pull down transistor and having a second threshold voltage greater than the first threshold voltage.

Abstract translation: 提供了包括具有附加读取堆栈的SRAM单元的集成电路。 根据一个实施例，集成电路包括存储器单元的存储器存储阵列。 集成电路包括耦合到存储器存储阵列的每个存储单元的读取堆栈。 每个读取堆叠包括具有第一阈值电压的读取下拉晶体管和与读出的下拉晶体管串联耦合并且具有大于第一阈值电压的第二阈值电压的读取通道栅极晶体管。

公开(公告)号：US09368605B2

公开(公告)日：2016-06-14

申请号：US14011976

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Igor Lusetsky ,  Ralf van Bentum

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/792 ,  H01L21/28

CPC classification number: H01L27/11546 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal.

Abstract translation: 半导体结构包括分离栅极非易失性存储单元和高压晶体管。 所述非易失性存储单元包括有源区，设置在所述有源区上方的非易失性存储堆，设置在所述存储堆上方的控制栅电极，至少部分地设置在与所述存储堆叠相邻的有源区上方的选择栅电极和选择栅极 绝缘层。 高压晶体管包括有源区，栅电极和设置在有源区和栅电极之间的栅极绝缘层。 非易失性存储器件的选择栅极绝缘层和高压晶体管的栅极绝缘层至少部分地由相同的高k电介质材料形成。 非易失性存储器件的选择栅电极和高电压晶体管的栅电极至少部分地由相同的金属形成。

公开(公告)号：US20160163821A1

公开(公告)日：2016-06-09

申请号：US15041581

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括第一晶体管区域和第二晶体管区域上的第一晶体管区域，第二晶体管区域和二氧化硅层。 一层高k电介质材料沉积在二氧化硅层上。 在第二晶体管区域上形成第一金属层。 第一金属层不覆盖第一晶体管区域。 在形成第一金属层之后，在第一晶体管区域和第二晶体管区域上沉积第二金属层。 执行第一退火处理。 第一退火处理从第一晶体管区域上的二氧化硅层的一部分引发第二金属和二氧化硅之间的清除反应。 在退火处理之后，在第一晶体管区域上形成铁电晶体管电介质。

公开(公告)号：US20160064228A1

公开(公告)日：2016-03-03

申请号：US14471812

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Gunter Grasshoff

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/22

CPC classification number: H01L21/28291 ,  H01L21/28185 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/1159 ,  H01L27/11592 ,  H01L27/22 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region.

Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域。 在半导体结构上形成第一保护层。 第一保护层覆盖逻辑晶体管区域和输入/输出晶体管区域。 至少一部分铁电晶体管区域不被第一保护层覆盖。 在形成第一保护层之后，在半导体结构上沉积铁电晶体管电介质，将铁电晶体管电介质和第一保护层从逻辑晶体管区域和输入/输出晶体管区域，输入/输出晶体管电介质 形成在输入/输出晶体管区域上，并且在至少逻辑晶体管区域上形成逻辑晶体管电介质。

公开(公告)号：US20160035856A1

公开(公告)日：2016-02-04

申请号：US14445893

申请日：2014-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L29/51 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.

Abstract translation: 本文所述的说明性半导体结构包括包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域的衬底。 逻辑晶体管设置在逻辑晶体管区域。 逻辑晶体管包括栅极电介质和栅电极。 输入/输出晶体管设置在输入/输出晶体管区域。 输入/输出晶体管包括栅极电介质和栅电极。 输入/输出晶体管的栅极电介质具有比逻辑晶体管的栅极电介质更大的厚度。 铁电晶体管设置在铁电晶体管区域。 铁电晶体管包括铁电电介质和栅电极。 铁电电介质布置在铁电晶体管区域和铁电晶体管的栅电极之间。

公开(公告)号：US09536992B2

公开(公告)日：2017-01-03

申请号：US15041581

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/115 ,  H01L21/8238

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括第一晶体管区域和第二晶体管区域上的第一晶体管区域，第二晶体管区域和二氧化硅层。 一层高k电介质材料沉积在二氧化硅层上。 在第二晶体管区域上形成第一金属层。 第一金属层不覆盖第一晶体管区域。 在形成第一金属层之后，在第一晶体管区域和第二晶体管区域上沉积第二金属层。 执行第一退火处理。 第一退火处理从第一晶体管区域上的二氧化硅层的一部分引发第二金属和二氧化硅之间的清除反应。 在退火处理之后，在第一晶体管区域上形成铁电晶体管电介质。

公开(公告)号：US09412600B2

公开(公告)日：2016-08-09

申请号：US14471812

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Gunter Grasshoff

IPC: H01L21/28 ,  H01L27/22 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L21/28291 ,  H01L21/28185 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/1159 ,  H01L27/11592 ,  H01L27/22 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region.

Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域。 在半导体结构上形成第一保护层。 第一保护层覆盖逻辑晶体管区域和输入/输出晶体管区域。 至少一部分铁电晶体管区域不被第一保护层覆盖。 在形成第一保护层之后，在半导体结构上沉积铁电晶体管电介质，将铁电晶体管电介质和第一保护层从逻辑晶体管区域和输入/输出晶体管区域，输入/输出晶体管电介质 形成在输入/输出晶体管区域上，并且在至少逻辑晶体管区域上形成逻辑晶体管电介质。