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    METHODS AND STRUCTURES FOR MITIGATING ESD DURING WAFER BONDING
    1.
    发明申请
    METHODS AND STRUCTURES FOR MITIGATING ESD DURING WAFER BONDING 审中-公开

    公开(公告)号：US20190067217A1

    公开(公告)日：2019-02-28

    申请号：US15685564

    申请日：2017-08-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Luke England ,  Tanya Atanasova ,  Daniel Smith ,  Daniel Fisher ,  Sukeshwar Kannan

    IPC: H01L23/60 ,  H01L23/522 ,  H01L23/00

    Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.

    TSV redundancy scheme and architecture using decoder/encoder
    3.
    发明授权
    TSV redundancy scheme and architecture using decoder/encoder 有权
    TSV冗余方案和使用解码器/编码器的架构

    公开(公告)号：US09401312B1

    公开(公告)日：2016-07-26

    申请号：US14736769

    申请日：2015-06-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Sukeshwar Kannan ,  Kaushal Kannan

    IPC: H01L21/768 ,  H03K19/177 ,  H03K19/173 ,  H01L21/66

    CPC classification number: H03K19/17764 ,  G01R31/2853 ,  H01L22/14 ,  H03K19/1735 ,  H03K19/17736

    Abstract: A method of redirecting signal bits associated with or corresponding to defective TSVs of a TSV array to a row or a column of redundant TSVs in the TSV array using a 2:4 Decoder and 4:2 Encoder and the resulting device are provided. Embodiments include forming a TSV array between a bottom die and a top die of a 3D IC stack, the TSV array having a row and a column of redundant TSVs; identifying a defective TSV of the TSV array; determining whether to shift a signal bit associated with or corresponding to the defective TSV in a first and/or a second direction towards the row or the column of redundant TSVs; and shifting the signal bit in the first and/or the second direction until the signal bit has been redirected to the row or the column of redundant TSVs.

    Abstract translation: 提供了使用2：4解码器和4：2编码器将与TSV阵列的有缺陷TSV相关联或对应的信号位重定向到TSV阵列中的冗余TSV的行或列的方法，并且得到所述装置。 实施例包括在3D IC堆叠的底模和顶模之间形成TSV阵列，该TSV阵列具有一列和一列冗余TSV; 识别TSV阵列的有缺陷的TSV; 确定是否将与第一和/或第二方向上的有缺陷TSV相关联的信号位或对应于与残余TSV相对应的信号位朝着冗余TSV的行或列移位; 并且在第一和/或第二方向上移位信号位，直到信号位被重定向到冗余TSV的行或列。

    METHODS OF MANUFACTURING RF FILTERS
    4.
    发明申请
    METHODS OF MANUFACTURING RF FILTERS 审中-公开

    公开(公告)号：US20190267361A1

    公开(公告)日：2019-08-29

    申请号：US15907413

    申请日：2018-02-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Md. Sayed Kaysar Bin Rahim ,  Luke England ,  Sukeshwar Kannan

    IPC: H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L41/313 ,  H01L21/768 ,  H01L21/78 ,  H03H9/54 ,  H03H9/64 ,  H03H9/13 ,  H03H9/145 ,  H03H3/02 ,  H03H3/08

    Abstract: A product disclosed herein includes an RF filter die including an RF filter, a front side and a plurality of conductive bond pads conductively coupled to at least a portion of the RF filter, wherein at least a portion of the conductive bond pads is exposed on the front side of the RF filter die. The product also includes a TSV (Through-Substrate-Via) die that includes a plurality of conductive TSV contacts positioned on a back side of the TSV die and at least one conductive TSV (Through-Substrate-Via) structure that is conductively coupled to at least one of the plurality of conductive TSV contacts, wherein the back side of the TSV die is bonded to the front side of the RF filter such that the conductive bond pads on the RF filter die are conductively coupled to corresponding conductive TSV contacts positioned on the back side of the TSV die.

    TESTING MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUITS
    5.
    发明申请
    TESTING MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20190094294A1

    公开(公告)日：2019-03-28

    申请号：US15801380

    申请日：2017-11-02

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sukeshwar Kannan ,  Abhishek Koneru ,  Krishnendu Chakrabarty

    IPC: G01R31/28 ,  G01R31/27 ,  G01R31/319

    Abstract: Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.

    DFT structure for TSVs in 3D ICs while maintaining functional purpose
    8.
    发明授权
    DFT structure for TSVs in 3D ICs while maintaining functional purpose 有权
    DFT结构，用于3D IC中的TSV，同时保持功能目的

    公开(公告)号：US09460975B2

    公开(公告)日：2016-10-04

    申请号：US14611496

    申请日：2015-02-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Sukeshwar Kannan ,  Xiaoqiang Zhang ,  Shan Gao

    IPC: H01L21/66 ,  H01L21/768

    CPC classification number: H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/5256 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: Methods of testing TSVs using eFuse cells prior to and post bonding wafers in a 3D IC stack are provided. Embodiments include providing a wafer of a 3D IC stack, the wafer having thin and thick metal layers; forming first and second TSVs on the wafer, the first and second TSVs laterally separated; forming an eFuse cell between and separated from the first and second TSVs; forming a FF adjacent to the second TSV and on an opposite side of the second TSV from the eFuse cell; connecting the first TSV, the eFuse cell, the second TSV, and the FF in series in an electric circuit; and testing the first and second TSVs prior to bonding the wafer to a subsequent wafer in the 3D IC stack.

    Abstract translation: 提供了在3D IC堆叠中将晶片接合和贴合之后使用eFuse电池测试TSV的方法。 实施例包括提供3D IC堆叠的晶片，该晶片具有薄而厚的金属层; 在晶片上形成第一和第二TSV，第一和第二TSV横向分离; 在第一和第二TSV之间形成eFuse单元并在其间分离; 在第二TSV附近形成与第二TSV相对的FF与eFuse单元; 在电路中串联连接第一TSV，eFuse单元，第二TSV和FF; 以及在将晶片连接到3D IC堆叠中的后续晶片之前测试第一和第二TSV。

    Methods and structures for mitigating ESD during wafer bonding
    9.
    发明授权
    Methods and structures for mitigating ESD during wafer bonding 有权

    公开(公告)号：US10236263B1

    公开(公告)日：2019-03-19

    申请号：US15685564

    申请日：2017-08-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Luke England ,  Tanya Atanasova ,  Daniel Smith ,  Daniel Fisher ,  Sukeshwar Kannan

    IPC: H01L23/60 ,  H01L23/522 ,  H01L23/00

    Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.

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