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公开(公告)号：US20190067217A1
公开(公告)日：2019-02-28
申请号：US15685564
申请日：2017-08-24
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Luke England , Tanya Atanasova , Daniel Smith , Daniel Fisher , Sukeshwar Kannan
IPC: H01L23/60 , H01L23/522 , H01L23/00
Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.
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公开(公告)号：US10236263B1
公开(公告)日：2019-03-19
申请号：US15685564
申请日：2017-08-24
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Luke England , Tanya Atanasova , Daniel Smith , Daniel Fisher , Sukeshwar Kannan
IPC: H01L23/60 , H01L23/522 , H01L23/00
Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.
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公开(公告)号：US09159683B2
公开(公告)日：2015-10-13
申请号：US14176697
申请日：2014-02-10
Applicant: GLOBALFOUNDRIES Inc. , Intermolecular Inc.
Inventor： Reiner Willeke , Tanya Atanasova , Anh Duong , Greg Nowling
IPC: H01L21/44 , H01L23/00 , H01L21/3213
CPC classification number: H01L24/11 , C23F1/02 , C23F1/26 , C23F1/34 , C23F1/44 , H01L21/32134 , H01L21/32139 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03614 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11848 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/13091 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/014 , H01L2924/01082 , H01L2924/01047 , H01L2924/0103 , H01L2924/01083 , H01L2924/01049 , H01L2924/01079 , H01L2924/01029 , H01L2924/01051 , H01L2924/00011 , H01L2924/00012 , H01L2924/04953 , H01L2924/04941
Abstract: Methods for etching copper in the fabrication of integrated circuits are disclosed. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing an integrated circuit structure including a copper bump structure and a copper seed layer underlying and adjacent to the copper bump structure and etching the seed layer selective to the copper bump structure using a wet etching chemistry consisting of H3PO4 in a volume percentage of about 0.07 to about 0.36, H2O2 in a volume percentage of about 0.1 to about 0.7, and a remainder of H2O, and optionally NH4OH.
Abstract translation: 公开了在制造集成电路中蚀刻铜的方法。 在一个示例性实施例中，一种用于制造集成电路的方法包括提供集成电路结构，该集成电路结构包括铜凸块结构和位于铜凸块结构之下并与铜凸起结构相邻的铜籽晶层，并使用湿法蚀刻对铜凸块结构有选择性的晶种层 以约0.07至约0.36的体积百分比由H 3 PO 4组成的体积百分比为约0.1至约0.7的H 2 O 2，以及剩余的H 2 O和任选的NH 4 OH的蚀刻化学。
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4.发明申请公开(公告)号：US20150228595A1
公开(公告)日：2015-08-13
申请号：US14176697
申请日：2014-02-10
Applicant: Intermolecular Inc. , GLOBALFOUNDRIES Inc.
Inventor： Reiner Willeke , Tanya Atanasova , Anh Duong , Greg Nowling
IPC: H01L23/00 , H01L21/3213
CPC classification number: H01L24/11 , C23F1/02 , C23F1/26 , C23F1/34 , C23F1/44 , H01L21/32134 , H01L21/32139 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03614 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11848 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/13091 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/014 , H01L2924/01082 , H01L2924/01047 , H01L2924/0103 , H01L2924/01083 , H01L2924/01049 , H01L2924/01079 , H01L2924/01029 , H01L2924/01051 , H01L2924/00011 , H01L2924/00012 , H01L2924/04953 , H01L2924/04941
Abstract: Methods for etching copper in the fabrication of integrated circuits are disclosed. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing an integrated circuit structure including a copper bump structure and a copper seed layer underlying and adjacent to the copper bump structure and etching the seed layer selective to the copper bump structure using a wet etching chemistry consisting of H3PO4 in a volume percentage of about 0.07 to about 0.36, H2O2 in a volume percentage of about 0.1 to about 0.7, and a remainder of H2O, and optionally NH4OH.
Abstract translation: 公开了在制造集成电路中蚀刻铜的方法。 在一个示例性实施例中，一种用于制造集成电路的方法包括提供集成电路结构，该集成电路结构包括铜凸块结构和位于铜凸块结构之下并与铜凸起结构相邻的铜籽晶层，并使用湿法蚀刻对铜凸块结构有选择性的晶种层 以约0.07至约0.36的体积百分比由H 3 PO 4组成的体积百分比为约0.1至约0.7的H 2 O 2，以及剩余的H 2 O和任选的NH 4 OH的蚀刻化学。
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