公开(公告)号：US20170345834A1

公开(公告)日：2017-11-30

申请号：US15163785

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Melde

IPC: H01L27/11524 ,  H01L29/06 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L29/40114 ,  H01L27/11536 ,  H01L27/1203 ,  H01L29/4234 ,  H01L29/66825

Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, and forming a memory device on the SOI substrate including forming a floating gate from a part of the semiconductor layer, forming an insulating layer on the floating gate, and forming a control gate on the insulating layer.

公开(公告)号：US10079242B2

公开(公告)日：2018-09-18

申请号：US15366425

申请日：2016-12-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Thomas Melde ,  Elke Erben

IPC: H01L29/10 ,  H01L27/11568 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L27/11573 ,  H01L21/033 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/11568 ,  H01L21/84 ,  H01L27/11573 ,  H01L27/1203 ,  H01L27/1237 ,  H01L29/0649 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7841 ,  H01L29/78654 ,  H01L29/78684 ,  H01L2029/42388

Abstract: Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.

公开(公告)号：US20170235867A1

公开(公告)日：2017-08-17

申请号：US15045466

申请日：2016-02-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Melde ,  Matthias U. Lehr ,  Thomas Herrmann ,  Jens Hassmann ,  Moritz Andreas Meyer ,  Rakesh Kumar Kuncha

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.

公开(公告)号：US20180158835A1

公开(公告)日：2018-06-07

申请号：US15366425

申请日：2016-12-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Thomas Melde ,  Elke Erben

IPC: H01L27/11568 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L27/11573 ,  H01L21/033 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/0332 ,  H01L21/28185 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/518

Abstract: Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.

公开(公告)号：US09898572B2

公开(公告)日：2018-02-20

申请号：US15045466

申请日：2016-02-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Melde ,  Matthias U. Lehr ,  Thomas Herrmann ,  Jens Hassmann ,  Moritz Andreas Meyer ,  Rakesh Kumar Kuncha

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.

公开(公告)号：US09842845B1

公开(公告)日：2017-12-12

申请号：US15337441

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Melde ,  Ralf Richter

IPC: H01L29/788 ,  H01L29/792 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L29/49

CPC classification number: H01L27/11531 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/31111 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: The present disclosure provides a semiconductor device structure including a non-volatile memory (NVM) device structure in and above a first region of a semiconductor substrate and a logic device formed in and above a second region of the semiconductor substrate different from the first region. The NVM device structure includes a floating-gate, a first select gate and at least one control gate. The logic device includes a logic gate disposed on the second region and source/drain regions provided in the second region adjacent to the logic gate. The control gate extends over the floating-gate and the first select gate is laterally separated from the floating-gate by an insulating material layer portion. Upon forming the semiconductor device structure, the floating gate is formed before forming the control gate and the logic device.